Added reset on PB(0)

fpga-logi · Oct 23, 2015 · 481f61b · 481f61b
1 parent c03ff2f
commit 481f61b
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/logi-camera-demo/hw/logibone/hdl/logibone_camera.vhd b/logi-camera-demo/hw/logibone/hdl/logibone_camera.vhd
@@ -153,8 +153,8 @@ begin
 	ARD_SCL <= 'Z' ;
 	ARD_SDA <= 'Z' ;
 
-	sys_resetn <= clk_locked ;
-	sys_reset <= not clk_locked ;
+	sys_resetn <= clk_locked AND PB(0);
+	sys_reset <= not sys_resetn ;
 	clk_sys <= clk_100 ;
 
 	divider : simple_counter