Add INBUF as recognized cell for wa.py

Signed-off-by: Eddie Hung <[email protected]>
eddieh-xlnx · Dec 5, 2023 · cafc974 · cafc974
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diff --git a/docs/score.md b/docs/score.md
@@ -119,7 +119,7 @@ BEL input and output pins for each type of PhysCell.
 |`LUT1`, `LUT2`, `LUT3`, `LUT4`, `LUT5`, `LUT6`                                            | (all) <- (all)                | Look Up Table      |
 |`CARRY8`                                                                                  | [see table CARRY8](#carry8-connectivity) | Fast Carry Logic |
 |`MUXF7`, `MUXF8`, `MUXF9`                                                                 | (all) <- (all)                | Intrasite Mux      |
-|`IBUFCTRL`                                                                                | (all) <- (all)                | Input Buffer       |
+|`IBUFCTRL`, `INBUF`                                                                       | (all) <- (all)                | Input Buffer       |
 |`DSP_A_B_DATA`, `DSP_C_DATA`, `DSP_M_DATA`,<br>`DSP_PREADD_DATA`, `DSP_OUTPUT`, `DSP_ALU` | (none) <- (none) [see note](#dsp-cell-connectivity) | DSP Logic |
 |`DSP_MULTIPLIER`, `DSP_PREADD`                                                            | (all) <- (all) [see note](#dsp-cell-connectivity) | DSP Logic |
 |`PCIE40E4`                                                                                | (none) <- (none)              | PCIe Hard Macro    |
@@ -130,7 +130,7 @@ BEL input and output pins for each type of PhysCell.
 | BEL output pin | BEL input pins                     |
 |------------|----------------------------------------|
 | `O0`       | `CIN`, `S0`                            |
-|`CO0`       | {input pins from `O0`} and `DI0`, `AX` |
+| `CO0`      | {input pins from `O0`} and `DI0`, `AX` |
 | `O1`       | {input pins from `CO0`} and `S1`       |
 | `CO1`      | {input pins from `O1`} and `DI1`, `BX` |
 | `O2`       | {input pins from `C01`} and `S2`       |

diff --git a/wirelength_analyzer/xcvup_device_data.py b/wirelength_analyzer/xcvup_device_data.py
@@ -79,6 +79,7 @@ def __contains__(self, item):
             'MUXF9':           self.all_to_all,
 
             'IBUFCTRL':        self.all_to_all,
+            'INBUF':           self.all_to_all,
 
             # The following cell types are BELs that make up a DSP macro.
             # Such DSPs contains a number of optional pipelining registers,