[Doc] Add "Inspecting Solutions Using Vivado" (#20)

* Add DcpToFPGAIF.java Signed-off-by: Eddie Hung <[email protected]> * Discover alternate sources Signed-off-by: Eddie Hung <[email protected]> * Add import, fix exit code Signed-off-by: Eddie Hung <[email protected]> * Update README.md * Update README.md * Update details.md * Update FAQ.md * Update README.md * Add "Inspecting Solutions using Vivado" section Signed-off-by: Eddie Hung <[email protected]> * Extend comment Signed-off-by: Eddie Hung <[email protected]> * Fix image Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]>
eddieh-xlnx · Oct 19, 2023 · b06a4da · b06a4da
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diff --git a/docs/start.md b/docs/start.md
@@ -213,6 +213,43 @@ Wall-clock time (sec): 168.94
 Displaying this output on screen in addition to writing to these logs can be achieved by setting
 the `VERBOSE` flag: `make VERBOSE=1`.
 
+### Inspecting Solutions using Vivado
+
+One can then open up the `vtr_mcml_nxroute-poc.dcp` in Vivado and run `report_route_status`
+explicitly:
+```
+Design Route Status
+                                               :      # nets :
+   ------------------------------------------- : ----------- :
+   # of logical nets.......................... :      190324 :
+       # of nets not needing routing.......... :      119342 :
+           # of internally routed nets........ :      107680 :
+           # of nets with no loads............ :       11554 :
+           # of implicitly routed ports....... :         108 :
+       # of routable nets..................... :       70982 :
+           # of unrouted nets................. :       54766 :
+           # of fully routed nets............. :        4647 :
+       # of nets with routing errors.......... :       11569 :
+           # of nets with some unrouted pins.. :         711 :
+           # of nets with resource conflicts.. :       11472 :
+   ------------------------------------------- : ----------- :
+```
+as well as to use its GUI to visualize resource conflicts, which may be helpful
+when debugging your own router. For example, executing the following command in the Tcl
+Console:
+```
+show_objects -name find_1 [get_nets -hierarchical -top_net_of_hierarchical_group -filter { ROUTE_STATUS == "CONFLICTS" } ]
+```
+will create a new tab containing all the conflicting nets.
+Clicking on a net will cause the Device view to select and zoom to that net (shown in white):
+
+[![image](vivado-conflict.png)](vivado-conflict.png)
+
+Note that the above screenshot above shows the Device view with the Unrouted Nets
+(red) and Partially Routed Nets (yellow) hidden from display.
+What remains are Fully Routed Nets (green) and Conflict Nets (dark magenta).
+Control of which net types are displayed can be accessed by clicking the blue "gear" icon
+in the top right of the GUI.
 
 ### Reference FPGAIF Physical Netlist Reader/Writer
 

diff --git a/docs/vivado-conflict.png b/docs/vivado-conflict.png
diff --git a/networkx-proof-of-concept-router/nxroute-poc.py b/networkx-proof-of-concept-router/nxroute-poc.py
@@ -408,6 +408,8 @@ def route(self):
                                 path = None
                                 # For every sink node, try all source nodes until one with a routing
                                 # path is found
+                                # Note that nx.shortest_path() only accepts a single source node; other
+                                # implementations may wish to consider all sources simultaneously
                                 for sourceNode in sourceNodes:
                                         try:
                                                 path = nx.shortest_path(self.G, sourceNode, sinkNode)