Merge branch 'Xilinx:master' into b

Makefile

@@ -96,7 +96,7 @@ fpga-interchange-schema/interchange/capnp/java.capnp:
 
 .PHONY: score-$(ROUTER)
 score-$(ROUTER): $(addsuffix _$(ROUTER).wirelength, $(BENCHMARKS)) $(addsuffix _$(ROUTER).check, $(BENCHMARKS))
-	python ./compute-score.py $(addsuffix _$(ROUTER), $(BENCHMARKS))
+	python3 ./compute-score.py $(addsuffix _$(ROUTER), $(BENCHMARKS))
 
 .PRECIOUS: %.device
 %.device: | compile-java

docs/score.md

@@ -114,12 +114,17 @@ BEL input and output pins for each type of PhysCell.
 |`RAMD32`, `RAMS32`                                                                        | `O5` and `O6` <- `A0` to `A4` | Distributed Memory |
 |`RAMD64E`, `RAMS64E`                                                                      | `O6` <- `A0` to `A5`          | Distributed Memory |
 |`RAMB36E2`, `RAMB18E2`                                                                    | (none) <- (none)              | Block Memory       |
+|`URAM288`                                                                                 | (none) <- (none)              | UltraRAM Memory    |
+|`MMCME4_ADV`                                                                              | (none) <- (none)              | Clock Manager      |
 |`LUT1`, `LUT2`, `LUT3`, `LUT4`, `LUT5`, `LUT6`                                            | (all) <- (all)                | Look Up Table      |
 |`CARRY8`                                                                                  | [see table CARRY8](#carry8-connectivity) | Fast Carry Logic |
 |`MUXF7`, `MUXF8`, `MUXF9`                                                                 | (all) <- (all)                | Intrasite Mux      |
 |`IBUFCTRL`                                                                                | (all) <- (all)                | Input Buffer       |
 |`DSP_A_B_DATA`, `DSP_C_DATA`, `DSP_M_DATA`,<br>`DSP_PREADD_DATA`, `DSP_OUTPUT`, `DSP_ALU` | (none) <- (none) [see note](#dsp-cell-connectivity) | DSP Logic |
 |`DSP_MULTIPLIER`, `DSP_PREADD`                                                            | (all) <- (all) [see note](#dsp-cell-connectivity) | DSP Logic |
+|`PCIE40E4`                                                                                | (none) <- (none)              | PCIe Hard Macro    |
+|`GTYE4_CHANNEL`,`GTYE4_COMMON`                                                            | (none) <- (none)              | Gigabit Transceiver Components |
+|`STARTUPE3`,`ICAPE3`                                                                      | (none) <- (none)              | Device Configuration Components |
 
 ### CARRY8 Connectivity
 | BEL output pin | BEL input pins                     |

src/com/xilinx/fpga24_routing_contest/PartialRouterPhysNetlist.java

@@ -44,11 +44,27 @@ public static void main(String[] args) throws IOException {
                 continue;
             }
             if (!net.hasPIPs()) {
+                // Route only nets with no PIPs
                 pinsToRoute.addAll(net.getSinkPins());
             }
         }
+
         boolean softPreserve = false;
-        PartialRouter.routeDesignPartialNonTimingDriven(design, pinsToRoute, softPreserve);
+        PartialRouter.routeDesignWithUserDefinedArguments(design, new String[] {
+                // Same options as PartialRouter.routeDesignPartialTimingDriven()
+                "--fixBoundingBox",
+                "--useUTurnNodes",
+                "--nonTimingDriven",
+                "--verbose",
+                // These options are set to their default value, a subset of which are duplicated here
+                // to ease modification; full documentation is available in RWRouteConfig.java
+                "--maxIterations", "100",
+                "--wirelengthWeight", "0.8",
+                "--initialPresentCongestionFactor", "0.5",
+                "--presentCongestionMultiplier", "2",
+                "--historicalCongestionFactor", "1",
+                },
+                pinsToRoute, softPreserve);
 
         // Write routed result to new Physical Netlist
         PhysNetlistWriter.writePhysNetlist(design, args[1]);

wirelength_analyzer/wa.py

@@ -108,6 +108,9 @@ def __init__(self, netlist, verbosity=0):
         xcvup = xcvupDeviceData()
         self.cells = xcvup.cells
         self.pips = xcvup.pips
+        self.tile_root_name_regex = xcvup.tile_root_name_regex
+        self.tile_types = xcvup.tile_types
+        self.global_net_drivers = xcvup.global_net_drivers
         self.pip_cache = {}
         self.tile_cache = {}
         if self.verbosity > 0:
@@ -116,7 +119,6 @@ def __init__(self, netlist, verbosity=0):
         self.placements = {}
         for c in self.phys.placements:
             self.placements[(c.site, c.bel)] = c
-        self.tile_root_name_regex = re.compile(r'(.+)_X\d+Y\d+')
         self.add_all_nets_to_graph()
 
     def tstart(self):
@@ -252,27 +254,25 @@ def segment_to_wirelength(self, seg):
             wire1 = seg.pip.wire1
             tile  = seg.pip.tile
             sl = self.phys.strList
+            wire1_name = sl[wire1]
+            tile_name = sl[tile]
 
             is_int_tile = self.tile_cache.get(tile)
             if is_int_tile is None:
-                tile_name = sl[tile]
                 is_int_tile = tile_name.startswith('INT_')
                 self.tile_cache[tile] = is_int_tile
-                if not is_int_tile and self.tile_root_name_regex.match(tile_name).group(1) not in \
-                    ('CLEL_R', 'CLEM', 'CLEM_R', 'BRAM', 'DSP',
-                     'XIPHY_BYTE_L', 'HPIO_L', 'CMT_L'):
-                    raise ValueError("Unrecognized tile on PIP: " + tile_name + ',' +  sl[seg.pip.wire0] + ',' + sl[wire1])
+                if not is_int_tile and self.tile_root_name_regex.match(tile_name).group(1) not in self.tile_types:
+                    raise ValueError("Unrecognized tile on PIP: " + tile_name + ',' +  sl[seg.pip.wire0] + ',' + wire1_name)
 
             if is_int_tile:
                 wl = self.pip_cache.get(wire1)
                 if wl is not None:
                     return wl
-                wire1_name = sl[wire1]
                 for p in self.pips:
                     if p[0].fullmatch(wire1_name):
                         self.pip_cache[wire1] = p[1]
                         return p[1]
-                assert False, "Found unrecognized pip wire1: "+wire1_name+" in tile: "+tile
+                assert False, "Found unrecognized pip wire1: "+wire1_name+" in tile: "+tile_name
             else:
                 return 0
         return 0
@@ -355,7 +355,7 @@ def add_all_nets_to_graph(self):
                 # Omit source (BELPins) that don't have any fanout
                 if len(branch.branches) == 0:
                     continue
-                if sl[branch.routeSegment.belPin.bel] in ('BUFCE'):
+                if sl[branch.routeSegment.belPin.bel] in self.global_net_drivers:
                     # don't analyze global (e.g. clk, rst) nets
                     if self.verbosity > 1:
                         print("Skipping global net:",this_net)

wirelength_analyzer/xcvup_device_data.py

@@ -36,10 +36,10 @@ def __contains__(self, item):
 
         self.cells = {
             # sequential
-            'FDRE':            self.default_sequential,
-            'FDCE':            self.default_sequential,
-            'FDSE':            self.default_sequential,
-            'FDPE':            self.default_sequential,
+            'FDRE':            self.none_to_none,
+            'FDCE':            self.none_to_none,
+            'FDSE':            self.none_to_none,
+            'FDPE':            self.none_to_none,
 
             'SRL16E':          self.srl16e,
             'SRLC32E':         self.srlc32e,
@@ -50,39 +50,50 @@ def __contains__(self, item):
             'RAMD64E':         self.ram_64e,
             'RAMS64E':         self.ram_64e,
 
-            'RAMB36E2':        self.default_sequential,
-            'RAMB18E2':        self.default_sequential,
+            'RAMB36E2':        self.none_to_none,
+            'RAMB18E2':        self.none_to_none,
+
+            'MMCME4_ADV':      self.none_to_none,
+
+            'URAM288':         self.none_to_none,
+
+            'GTYE4_CHANNEL':   self.none_to_none,
+            'GTYE4_COMMON':    self.none_to_none,
+            'PCIE40E4':        self.none_to_none,
+
+            'STARTUPE3':       self.none_to_none,
+            'ICAPE3':          self.none_to_none,
 
             # combinatorial
-            'LUT1':            self.default_combinatorial,
-            'LUT2':            self.default_combinatorial,
-            'LUT3':            self.default_combinatorial,
-            'LUT4':            self.default_combinatorial,
-            'LUT5':            self.default_combinatorial,
-            'LUT6':            self.default_combinatorial,
+            'LUT1':            self.all_to_all,
+            'LUT2':            self.all_to_all,
+            'LUT3':            self.all_to_all,
+            'LUT4':            self.all_to_all,
+            'LUT5':            self.all_to_all,
+            'LUT6':            self.all_to_all,
 
             'CARRY8':          self.carry8,
 
-            'MUXF7':           self.default_combinatorial,
-            'MUXF8':           self.default_combinatorial,
-            'MUXF9':           self.default_combinatorial,
+            'MUXF7':           self.all_to_all,
+            'MUXF8':           self.all_to_all,
+            'MUXF9':           self.all_to_all,
 
-            'IBUFCTRL':        self.default_combinatorial,
+            'IBUFCTRL':        self.all_to_all,
 
             # The following cell types are BELs that make up a DSP macro.
             # Such DSPs contains a number of optional pipelining registers,
             # but to determine whether such registers are enabled currently
             # requires examining the design's corresponding Logical Netlist.
             # For the purpose of the FPGA24 Routing Contest, we optimistically
             # assume that all BELs possessing a CLK pin are fully sequential.
-            'DSP_A_B_DATA':    self.default_sequential,
-            'DSP_C_DATA':      self.default_sequential,
-            'DSP_M_DATA':      self.default_sequential,
-            'DSP_PREADD_DATA': self.default_sequential,
-            'DSP_OUTPUT':      self.default_sequential,
-            'DSP_ALU':         self.default_sequential,
-            'DSP_MULTIPLIER':  self.default_combinatorial,
-            'DSP_PREADD':      self.default_combinatorial,
+            'DSP_A_B_DATA':    self.none_to_none,
+            'DSP_C_DATA':      self.none_to_none,
+            'DSP_M_DATA':      self.none_to_none,
+            'DSP_PREADD_DATA': self.none_to_none,
+            'DSP_OUTPUT':      self.none_to_none,
+            'DSP_ALU':         self.none_to_none,
+            'DSP_MULTIPLIER':  self.all_to_all,
+            'DSP_PREADD':      self.all_to_all,
         }
 
         # pip wirelengths are assigned based on the values provided in Table 1
@@ -97,6 +108,7 @@ def __contains__(self, item):
             (re.compile(r'INT_NODE_GLOBAL_\d{1,2}_INT_OUT[01]'),     0),
             (re.compile(r'IMUX_[EW]\d{1,2}'),                        0),
             (re.compile(r'IMUX_(CMT_)?XIPHY\d{1,2}'),                0),
+            (re.compile(r'IMUXOUT\d{1,2}'),                          0),
             (re.compile(r'CTRL_[EW][0-9]'),                          0),
             (re.compile(r'CLE_CLE_[LM]_SITE_0_[A-H](_O|MUX|Q(2)?)'), 0),
             (re.compile(r'BYPASS_[EW]\d{1,2}'),                      0),
@@ -135,15 +147,28 @@ def __contains__(self, item):
             (re.compile(r'CLK_LEAF_SITES_\d_CLK_LEAF'),              0),
         ]
 
-    def default_sequential(self, o):
+        # recognized tile types and regex to strip tile location
+        self.tile_root_name_regex = re.compile(r'(.+)_X\d+Y\d+')
+        self.tile_types = {
+            'CLEL_R', 'CLEM', 'CLEM_R', 'BRAM', 'DSP', 'XIPHY_BYTE_L',
+            'HPIO_L', 'CMT_L', 'URAM_URAM_FT', 'URAM_URAM_DELAY_FT', 'GTY_L',
+            'GTY_R'
+        }
+
+        # bels that drive global nets
+        self.global_net_drivers = {
+            'BUFCE', 'BUFG_GT', 'BUFG_GT_SYNC'
+        }
+
+    def none_to_none(self, o):
         """
         Default connectivity for combinatorial logic
 
         The set of connections from all inputs to any output is the empty set
         """
         return self.empty
 
-    def default_combinatorial(self, o):
+    def all_to_all(self, o):
         """
         Default connectivity for combinatorial logic