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Fix clippy warnings #272

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Feb 25, 2025
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8 changes: 4 additions & 4 deletions src/devices/src/virtio/balloon/device.rs
Original file line number Diff line number Diff line change
Expand Up @@ -28,10 +28,10 @@ pub(crate) const PHQ_INDEX: usize = 3;
pub(crate) const FRQ_INDEX: usize = 4;

// Supported features.
pub(crate) const AVAIL_FEATURES: u64 = 1 << uapi::VIRTIO_F_VERSION_1 as u64
| 1 << uapi::VIRTIO_BALLOON_F_STATS_VQ as u64
| 1 << uapi::VIRTIO_BALLOON_F_FREE_PAGE_HINT as u64
| 1 << uapi::VIRTIO_BALLOON_F_REPORTING as u64;
pub(crate) const AVAIL_FEATURES: u64 = (1 << uapi::VIRTIO_F_VERSION_1 as u64)
| (1 << uapi::VIRTIO_BALLOON_F_STATS_VQ as u64)
| (1 << uapi::VIRTIO_BALLOON_F_FREE_PAGE_HINT as u64)
| (1 << uapi::VIRTIO_BALLOON_F_REPORTING as u64);

#[derive(Copy, Clone, Debug, Default)]
#[repr(C, packed)]
Expand Down
6 changes: 3 additions & 3 deletions src/devices/src/virtio/console/device.rs
Original file line number Diff line number Diff line change
Expand Up @@ -30,9 +30,9 @@ use crate::virtio::{PortDescription, VmmExitObserver};
pub(crate) const CONTROL_RXQ_INDEX: usize = 2;
pub(crate) const CONTROL_TXQ_INDEX: usize = 3;

pub(crate) const AVAIL_FEATURES: u64 = 1 << uapi::VIRTIO_CONSOLE_F_SIZE as u64
| 1 << uapi::VIRTIO_CONSOLE_F_MULTIPORT as u64
| 1 << uapi::VIRTIO_F_VERSION_1 as u64;
pub(crate) const AVAIL_FEATURES: u64 = (1 << uapi::VIRTIO_CONSOLE_F_SIZE as u64)
| (1 << uapi::VIRTIO_CONSOLE_F_MULTIPORT as u64)
| (1 << uapi::VIRTIO_F_VERSION_1 as u64);

#[repr(C)]
#[derive(Default)]
Expand Down
10 changes: 5 additions & 5 deletions src/devices/src/virtio/gpu/device.rs
Original file line number Diff line number Diff line change
Expand Up @@ -26,11 +26,11 @@ pub(crate) const CTL_INDEX: usize = 0;
pub(crate) const CUR_INDEX: usize = 1;

// Supported features.
pub(crate) const AVAIL_FEATURES: u64 = 1u64 << uapi::VIRTIO_F_VERSION_1
| 1u64 << uapi::VIRTIO_GPU_F_VIRGL
| 1u64 << uapi::VIRTIO_GPU_F_RESOURCE_UUID
| 1u64 << uapi::VIRTIO_GPU_F_RESOURCE_BLOB
| 1u64 << uapi::VIRTIO_GPU_F_CONTEXT_INIT;
pub(crate) const AVAIL_FEATURES: u64 = (1u64 << uapi::VIRTIO_F_VERSION_1)
| (1u64 << uapi::VIRTIO_GPU_F_VIRGL)
| (1u64 << uapi::VIRTIO_GPU_F_RESOURCE_UUID)
| (1u64 << uapi::VIRTIO_GPU_F_RESOURCE_BLOB)
| (1u64 << uapi::VIRTIO_GPU_F_CONTEXT_INIT);

pub struct Gpu {
pub(crate) queue_ctl: Arc<Mutex<VirtQueue>>,
Expand Down
18 changes: 9 additions & 9 deletions src/devices/src/virtio/net/device.rs
Original file line number Diff line number Diff line change
Expand Up @@ -93,15 +93,15 @@ pub struct Net {
impl Net {
/// Create a new virtio network device using the backend
pub fn new(id: String, cfg_backend: VirtioNetBackend, mac: [u8; 6]) -> Result<Self> {
let avail_features = 1 << VIRTIO_NET_F_GUEST_CSUM
| 1 << VIRTIO_NET_F_CSUM
| 1 << VIRTIO_NET_F_GUEST_TSO4
| 1 << VIRTIO_NET_F_HOST_TSO4
| 1 << VIRTIO_NET_F_GUEST_UFO
| 1 << VIRTIO_NET_F_HOST_UFO
| 1 << VIRTIO_NET_F_MAC
| 1 << VIRTIO_RING_F_EVENT_IDX
| 1 << VIRTIO_F_VERSION_1;
let avail_features = (1 << VIRTIO_NET_F_GUEST_CSUM)
| (1 << VIRTIO_NET_F_CSUM)
| (1 << VIRTIO_NET_F_GUEST_TSO4)
| (1 << VIRTIO_NET_F_HOST_TSO4)
| (1 << VIRTIO_NET_F_GUEST_UFO)
| (1 << VIRTIO_NET_F_HOST_UFO)
| (1 << VIRTIO_NET_F_MAC)
| (1 << VIRTIO_RING_F_EVENT_IDX)
| (1 << VIRTIO_F_VERSION_1);

let mut queue_evts = Vec::new();
for _ in QUEUE_SIZES.iter() {
Expand Down
6 changes: 3 additions & 3 deletions src/devices/src/virtio/queue.rs
Original file line number Diff line number Diff line change
Expand Up @@ -395,7 +395,7 @@ impl Queue {
false
} else if desc_table
.checked_add(desc_table_size)
.map_or(true, |v| !mem.address_in_range(v))
.is_none_or(|v| !mem.address_in_range(v))
{
error!(
"virtio queue descriptor table goes out of bounds: start:0x{:08x} size:0x{:08x}",
Expand All @@ -405,7 +405,7 @@ impl Queue {
false
} else if avail_ring
.checked_add(avail_ring_size)
.map_or(true, |v| !mem.address_in_range(v))
.is_none_or(|v| !mem.address_in_range(v))
{
error!(
"virtio queue available ring goes out of bounds: start:0x{:08x} size:0x{:08x}",
Expand All @@ -415,7 +415,7 @@ impl Queue {
false
} else if used_ring
.checked_add(used_ring_size)
.map_or(true, |v| !mem.address_in_range(v))
.is_none_or(|v| !mem.address_in_range(v))
{
error!(
"virtio queue used ring goes out of bounds: start:0x{:08x} size:0x{:08x}",
Expand Down
24 changes: 12 additions & 12 deletions src/devices/src/virtio/snd/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -41,18 +41,18 @@ mod defs {
pub const RXQ_INDEX: usize = 3;
pub const QUEUE_INDEXES: [usize; 4] = [CTL_INDEX, EVT_INDEX, TXQ_INDEX, RXQ_INDEX];

pub const SUPPORTED_FORMATS: u64 = 1 << VIRTIO_SND_PCM_FMT_U8
| 1 << VIRTIO_SND_PCM_FMT_S16
| 1 << VIRTIO_SND_PCM_FMT_S24
| 1 << VIRTIO_SND_PCM_FMT_S32;

pub const SUPPORTED_RATES: u64 = 1 << VIRTIO_SND_PCM_RATE_8000
| 1 << VIRTIO_SND_PCM_RATE_11025
| 1 << VIRTIO_SND_PCM_RATE_16000
| 1 << VIRTIO_SND_PCM_RATE_22050
| 1 << VIRTIO_SND_PCM_RATE_32000
| 1 << VIRTIO_SND_PCM_RATE_44100
| 1 << VIRTIO_SND_PCM_RATE_48000;
pub const SUPPORTED_FORMATS: u64 = (1 << VIRTIO_SND_PCM_FMT_U8)
| (1 << VIRTIO_SND_PCM_FMT_S16)
| (1 << VIRTIO_SND_PCM_FMT_S24)
| (1 << VIRTIO_SND_PCM_FMT_S32);

pub const SUPPORTED_RATES: u64 = (1 << VIRTIO_SND_PCM_RATE_8000)
| (1 << VIRTIO_SND_PCM_RATE_11025)
| (1 << VIRTIO_SND_PCM_RATE_16000)
| (1 << VIRTIO_SND_PCM_RATE_22050)
| (1 << VIRTIO_SND_PCM_RATE_32000)
| (1 << VIRTIO_SND_PCM_RATE_44100)
| (1 << VIRTIO_SND_PCM_RATE_48000);

pub mod uapi {
pub const VIRTIO_F_VERSION_1: u32 = 32;
Expand Down
6 changes: 3 additions & 3 deletions src/devices/src/virtio/vsock/device.rs
Original file line number Diff line number Diff line change
Expand Up @@ -33,9 +33,9 @@ pub(crate) const EVQ_INDEX: usize = 2;
/// - VIRTIO_F_VERSION_1: the device conforms to at least version 1.0 of the VirtIO spec.
/// - VIRTIO_F_IN_ORDER: the device returns used buffers in the same order that the driver makes
/// them available.
pub(crate) const AVAIL_FEATURES: u64 = 1 << uapi::VIRTIO_F_VERSION_1 as u64
| 1 << uapi::VIRTIO_F_IN_ORDER as u64
| 1 << uapi::VIRTIO_VSOCK_F_DGRAM;
pub(crate) const AVAIL_FEATURES: u64 = (1 << uapi::VIRTIO_F_VERSION_1 as u64)
| (1 << uapi::VIRTIO_F_IN_ORDER as u64)
| (1 << uapi::VIRTIO_VSOCK_F_DGRAM);

pub struct Vsock {
cid: u64,
Expand Down
32 changes: 16 additions & 16 deletions src/devices/src/virtio/vsock/muxer.rs
Original file line number Diff line number Diff line change
Expand Up @@ -273,7 +273,7 @@ impl VsockMuxer {
match req._type {
defs::SOCK_STREAM => {
debug!("vsock: proxy create stream");
let id = (req.peer_port as u64) << 32 | defs::TSI_PROXY_PORT as u64;
let id = ((req.peer_port as u64) << 32) | (defs::TSI_PROXY_PORT as u64);
match TcpProxy::new(
id,
self.cid,
Expand All @@ -295,7 +295,7 @@ impl VsockMuxer {
}
defs::SOCK_DGRAM => {
debug!("vsock: proxy create dgram");
let id = (req.peer_port as u64) << 32 | defs::TSI_PROXY_PORT as u64;
let id = ((req.peer_port as u64) << 32) | (defs::TSI_PROXY_PORT as u64);
match UdpProxy::new(
id,
self.cid,
Expand All @@ -321,7 +321,7 @@ impl VsockMuxer {
fn process_connect(&self, pkt: &VsockPacket) {
debug!("vsock: proxy connect request");
if let Some(req) = pkt.read_connect_req() {
let id = (req.peer_port as u64) << 32 | defs::TSI_PROXY_PORT as u64;
let id = ((req.peer_port as u64) << 32) | (defs::TSI_PROXY_PORT as u64);
debug!("vsock: proxy connect request: id={}", id);
let update = self
.proxy_map
Expand All @@ -339,7 +339,7 @@ impl VsockMuxer {
fn process_getname(&self, pkt: &VsockPacket) {
debug!("vsock: new getname request");
if let Some(req) = pkt.read_getname_req() {
let id = (req.peer_port as u64) << 32 | (req.local_port as u64);
let id = ((req.peer_port as u64) << 32) | (req.local_port as u64);
debug!(
"vsock: new getname request: id={}, peer_port={}, local_port={}",
id, req.peer_port, req.local_port
Expand All @@ -354,7 +354,7 @@ impl VsockMuxer {
fn process_sendto_addr(&self, pkt: &VsockPacket) {
debug!("vsock: new DGRAM sendto addr: src={}", pkt.src_port());
if let Some(req) = pkt.read_sendto_addr() {
let id = (req.peer_port as u64) << 32 | defs::TSI_PROXY_PORT as u64;
let id = ((req.peer_port as u64) << 32) | (defs::TSI_PROXY_PORT as u64);
debug!("vsock: new DGRAM sendto addr: id={}", id);
let update = self
.proxy_map
Expand All @@ -370,7 +370,7 @@ impl VsockMuxer {
}

fn process_sendto_data(&self, pkt: &VsockPacket) {
let id = (pkt.src_port() as u64) << 32 | defs::TSI_PROXY_PORT as u64;
let id = ((pkt.src_port() as u64) << 32) | (defs::TSI_PROXY_PORT as u64);
debug!("vsock: DGRAM sendto data: id={} src={}", id, pkt.src_port());
if let Some(proxy) = self.proxy_map.read().unwrap().get(&id) {
proxy.lock().unwrap().sendto_data(pkt);
Expand All @@ -380,7 +380,7 @@ impl VsockMuxer {
fn process_listen_request(&self, pkt: &VsockPacket) {
debug!("vsock: DGRAM listen request: src={}", pkt.src_port());
if let Some(req) = pkt.read_listen_req() {
let id = (req.peer_port as u64) << 32 | defs::TSI_PROXY_PORT as u64;
let id = ((req.peer_port as u64) << 32) | (defs::TSI_PROXY_PORT as u64);
debug!("vsock: DGRAM listen request: id={}", id);
let update = self
.proxy_map
Expand All @@ -398,7 +398,7 @@ impl VsockMuxer {
fn process_accept_request(&self, pkt: &VsockPacket) {
debug!("vsock: DGRAM accept request: src={}", pkt.src_port());
if let Some(req) = pkt.read_accept_req() {
let id = (req.peer_port as u64) << 32 | defs::TSI_PROXY_PORT as u64;
let id = ((req.peer_port as u64) << 32) | (defs::TSI_PROXY_PORT as u64);
debug!("vsock: DGRAM accept request: id={}", id);
let update = self
.proxy_map
Expand All @@ -416,7 +416,7 @@ impl VsockMuxer {
fn process_proxy_release(&self, pkt: &VsockPacket) {
debug!("vsock: DGRAM release request: src={}", pkt.src_port());
if let Some(req) = pkt.read_release_req() {
let id = (req.peer_port as u64) << 32 | req.local_port as u64;
let id = ((req.peer_port as u64) << 32) | (req.local_port as u64);
debug!(
"vsock: DGRAM release request: id={} local_port={} peer_port={}",
id, req.local_port, req.peer_port
Expand Down Expand Up @@ -444,7 +444,7 @@ impl VsockMuxer {

fn process_dgram_rw(&self, pkt: &VsockPacket) {
debug!("vsock: DGRAM OP_RW");
let id = (pkt.src_port() as u64) << 32 | defs::TSI_PROXY_PORT as u64;
let id = ((pkt.src_port() as u64) << 32) | (defs::TSI_PROXY_PORT as u64);

if let Some(proxy_lock) = self.proxy_map.read().unwrap().get(&id) {
debug!("vsock: DGRAM allowing OP_RW for {}", pkt.src_port());
Expand Down Expand Up @@ -494,7 +494,7 @@ impl VsockMuxer {

fn process_op_request(&mut self, pkt: &VsockPacket) {
debug!("vsock: OP_REQUEST");
let id: u64 = (pkt.src_port() as u64) << 32 | pkt.dst_port() as u64;
let id: u64 = ((pkt.src_port() as u64) << 32) | (pkt.dst_port() as u64);
let mut proxy_map = self.proxy_map.write().unwrap();

if let Some(proxy) = proxy_map.get(&id) {
Expand Down Expand Up @@ -540,7 +540,7 @@ impl VsockMuxer {

fn process_op_response(&self, pkt: &VsockPacket) {
debug!("vsock: OP_RESPONSE");
let id: u64 = (pkt.src_port() as u64) << 32 | pkt.dst_port() as u64;
let id: u64 = ((pkt.src_port() as u64) << 32) | (pkt.dst_port() as u64);
let update = self
.proxy_map
.read()
Expand All @@ -565,15 +565,15 @@ impl VsockMuxer {

fn process_op_shutdown(&self, pkt: &VsockPacket) {
debug!("vsock: OP_SHUTDOWN");
let id: u64 = (pkt.src_port() as u64) << 32 | pkt.dst_port() as u64;
let id: u64 = ((pkt.src_port() as u64) << 32) | (pkt.dst_port() as u64);
if let Some(proxy) = self.proxy_map.read().unwrap().get(&id) {
proxy.lock().unwrap().shutdown(pkt);
}
}

fn process_op_credit_update(&self, pkt: &VsockPacket) {
debug!("vsock: OP_CREDIT_UPDATE");
let id: u64 = (pkt.src_port() as u64) << 32 | pkt.dst_port() as u64;
let id: u64 = ((pkt.src_port() as u64) << 32) | (pkt.dst_port() as u64);
let update = self
.proxy_map
.read()
Expand All @@ -587,7 +587,7 @@ impl VsockMuxer {

fn process_stream_rw(&self, pkt: &VsockPacket) {
debug!("vsock: OP_RW");
let id: u64 = (pkt.src_port() as u64) << 32 | pkt.dst_port() as u64;
let id: u64 = ((pkt.src_port() as u64) << 32) | (pkt.dst_port() as u64);
if let Some(proxy_lock) = self.proxy_map.read().unwrap().get(&id) {
debug!(
"vsock: allowing OP_RW: src={} dst={}",
Expand Down Expand Up @@ -625,7 +625,7 @@ impl VsockMuxer {

fn process_stream_rst(&self, pkt: &VsockPacket) {
debug!("vsock: OP_RST");
let id: u64 = (pkt.src_port() as u64) << 32 | pkt.dst_port() as u64;
let id: u64 = ((pkt.src_port() as u64) << 32) | (pkt.dst_port() as u64);
if let Some(proxy_lock) = self.proxy_map.read().unwrap().get(&id) {
debug!(
"vsock: allowing OP_RST: id={} src={} dst={}",
Expand Down
4 changes: 2 additions & 2 deletions src/devices/src/virtio/vsock/muxer_thread.rs
Original file line number Diff line number Diff line change
Expand Up @@ -120,7 +120,7 @@ impl MuxerThread {

if let Some((peer_port, accept_fd, proxy_type)) = update.new_proxy {
let local_port: u32 = thread_rng.gen_range(1024..u32::MAX);
let new_id: u64 = (peer_port as u64) << 32 | local_port as u64;
let new_id: u64 = ((peer_port as u64) << 32) | (local_port as u64);
let new_proxy: Box<dyn Proxy> = match proxy_type {
NewProxyType::Tcp => Box::new(TcpProxy::new_reverse(
new_id,
Expand Down Expand Up @@ -171,7 +171,7 @@ impl MuxerThread {
if !do_listen {
continue;
}
let id = (*port as u64) << 32 | defs::TSI_PROXY_PORT as u64;
let id = ((*port as u64) << 32) | (defs::TSI_PROXY_PORT as u64);
let proxy = match UnixAcceptorProxy::new(id, path, *port) {
Ok(proxy) => proxy,
Err(e) => {
Expand Down
2 changes: 1 addition & 1 deletion src/rutabaga_gfx/src/rutabaga_gralloc/formats.rs
Original file line number Diff line number Diff line change
Expand Up @@ -109,7 +109,7 @@ impl DrmFormat {
/// Constructs a format identifer using a fourcc byte sequence.
#[inline(always)]
pub fn new(a: u8, b: u8, c: u8, d: u8) -> DrmFormat {
DrmFormat(a as u32 | (b as u32) << 8 | (c as u32) << 16 | (d as u32) << 24)
DrmFormat((a as u32) | ((b as u32) << 8) | ((c as u32) << 16) | ((d as u32) << 24))
}

/// Returns the fourcc code as a sequence of bytes.
Expand Down
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