add newlines at EOF

.cargo/config.toml

@@ -4,4 +4,4 @@
 
 [build]
 target = "riscv32imc-unknown-none-elf"
-rustflags = ["-C", "target-feature=+f"]
+rustflags = ["-C", "target-feature=+f"]

.github/workflows/ci.yml

@@ -158,4 +158,4 @@ jobs:
           tar -x -f vexriscv-test-binaries.tar
       - name: Run unittests
         run: |
-          cabal run clash-vexriscv-sim:unittests
+          cabal run clash-vexriscv-sim:unittests

.gitignore

@@ -64,4 +64,4 @@ vivado.jou
 log
 vivado_*
 tight_setup_hold_pins.txt
-.Xil
+.Xil

cabal.project

@@ -54,4 +54,4 @@ source-repository-package
 source-repository-package
   type: git
   location: https://github.com/cchalmers/circuit-notation.git
-  tag: 618e37578e699df235f2e7150108b6401731919b
+  tag: 618e37578e699df235f2e7150108b6401731919b

clash-vexriscv-sim/app/Clash.hs

@@ -7,4 +7,4 @@ import System.Environment (getArgs)
 import Clash.Main (defaultMain)
 
 main :: IO ()
-main = getArgs >>= defaultMain
+main = getArgs >>= defaultMain

clash-vexriscv-sim/app/HdlTest.hs

@@ -18,4 +18,4 @@ circuit clk rst input =
 makeTopEntity 'circuit
 
 main :: IO ()
-main = pure ()
+main = pure ()

clash-vexriscv-sim/src/Utils/Cpu.hs

@@ -144,4 +144,4 @@ dummyWb m2s' = delayControls m2s' (reply <$> m2s')
           (\wb newAck newErr -> wb {acknowledge = newAck, err = newErr})
             <$> s2m0
             <*> delayedAck
-            <*> delayedErr1
+            <*> delayedErr1

clash-vexriscv-sim/src/Utils/Interconnect.hs

@@ -41,4 +41,4 @@ interconnectTwo m2s ((aAddr', aS2M') :> (bAddr', bS2M') :> Nil) =
       | otherwise     =
           ( emptyWishboneS2M { err = True },
             emptyWishboneM2S :> emptyWishboneM2S :> Nil
-          )
+          )

clash-vexriscv-sim/src/Utils/ProgramLoad.hs

@@ -56,4 +56,4 @@ loadProgram path = do
     chunkFill n fill xs =
       let (first0, rest) = L.splitAt n xs
           first1 = first0 <> L.replicate (n - L.length first0) fill
-       in first1 : chunkFill n fill rest
+       in first1 : chunkFill n fill rest

clash-vexriscv-sim/src/Utils/Storage.hs

@@ -90,4 +90,4 @@ writeDataSel mem addr sel val =
     _ -> mem
 
   where
-    (hh :: BitVector 8, hl :: BitVector 8, lh :: BitVector 8, ll :: BitVector 8) = unpack val
+    (hh :: BitVector 8, hl :: BitVector 8, lh :: BitVector 8, ll :: BitVector 8) = unpack val

clash-vexriscv-sim/test-programs/src/bin/ebreak_exception.expected

@@ -1,2 +1,2 @@
 Executing `ebreak` instruction...
-... caught an exception. Looping forever now.
+... caught an exception. Looping forever now.

clash-vexriscv-sim/test-programs/src/bin/fpu_test.expected

@@ -3,4 +3,4 @@ This test makes sure the FPU works as expected
 1.3 + 5.3 = 6.6000004
 5.3 - 1.3 = 4
 24.65 * 43.2 = 1064.88
-12.6 / 4.2 = 3.0000002
+12.6 / 4.2 = 3.0000002

clash-vexriscv/example-cpu/VexRiscv.v.license

@@ -1,3 +1,3 @@
 SPDX-FileCopyrightText: 2023 Google LLC
 
-SPDX-License-Identifier: Apache-2.0
+SPDX-License-Identifier: Apache-2.0

clash-vexriscv/src/VexRiscv/TH.hs

@@ -71,4 +71,4 @@ findCabalPackage pkgName = goUp =<< canonicalizePath pkgName
       [c] -> pure c
 
   packageFilename = pkgName <> ".cabal"
-  projectFilename = "cabal.project"
+  projectFilename = "cabal.project"

rust-toolchain.toml

@@ -15,4 +15,4 @@
 channel = "1.67.1"
 targets = [ "riscv32imc-unknown-none-elf", "x86_64-unknown-linux-gnu" ]
 profile = "minimal"
-components = [ "clippy", "rustfmt" ]
+components = [ "clippy", "rustfmt" ]