Merge pull request #5 from clash-lang/f-extension

Add F extension to CPU

.cargo/config.toml

@@ -4,3 +4,4 @@
 
 [build]
 target = "riscv32imc-unknown-none-elf"
+rustflags = ["-C", "target-feature=+f"]

clash-vexriscv-sim/app/Clash.hs

@@ -0,0 +1,10 @@
+-- SPDX-FileCopyrightText: 2023 Google LLC
+--
+-- SPDX-License-Identifier: Apache-2.0
+
+import Prelude
+import System.Environment (getArgs)
+import Clash.Main (defaultMain)
+
+main :: IO ()
+main = getArgs >>= defaultMain

clash-vexriscv-sim/app/HdlTest.hs

@@ -0,0 +1,21 @@
+-- SPDX-FileCopyrightText: 2023 Google LLC
+--
+-- SPDX-License-Identifier: Apache-2.0
+
+import Clash.Prelude
+import Clash.Annotations.TH
+
+import VexRiscv
+
+circuit ::
+  "CLK" ::: Clock System ->
+  "RST" ::: Reset System ->
+  "INPUT" ::: Signal System Input ->
+  "OUTPUT" ::: Signal System Output
+circuit clk rst input =
+  withClockResetEnable clk rst enableGen vexRiscv input
+
+makeTopEntity 'circuit
+
+main :: IO ()
+main = pure ()

clash-vexriscv-sim/app/VexRiscvSimulation.hs

@@ -59,9 +59,9 @@ debugConfig =
 --
 {-
   InspectBusses
-    500
+    50
     0
-    (Just 150)
+    (Just 300)
     True
     True
 -- -}

clash-vexriscv-sim/clash-vexriscv-sim.cabal

@@ -85,6 +85,21 @@ library
     elf >= 0.31 && < 0.32,
     bytestring >= 0.10 && < 0.11,
 
+executable clash
+  import: common-options
+  main-is: app/Clash.hs
+  build-Depends: base, clash-ghc
+
+executable hdl-test
+  import: common-options
+  main-is: app/HdlTest.hs
+  build-Depends:
+    base,
+    clash-prelude,
+    clash-protocols,
+    clash-vexriscv,
+    clash-vexriscv-sim,
+
 executable clash-vexriscv-bin
   import: common-options
   main-is: VexRiscvSimulation.hs

clash-vexriscv-sim/test-programs/src/bin/fpu_test.expected

@@ -0,0 +1,6 @@
+This test makes sure the FPU works as expected
+79823i32 as f32 = 79823
+1.3 + 5.3 = 6.6000004
+5.3 - 1.3 = 4
+24.65 * 43.2 = 1064.88
+12.6 / 4.2 = 3.0000002

clash-vexriscv-sim/test-programs/src/bin/fpu_test.rs

@@ -0,0 +1,54 @@
+// SPDX-FileCopyrightText: 2022 Google LLC
+//
+// SPDX-License-Identifier: Apache-2.0
+
+#![no_std]
+#![cfg_attr(not(test), no_main)]
+
+use core::fmt::Write;
+
+#[cfg(not(test))]
+use riscv_rt::entry;
+
+#[cfg(not(test))]
+extern crate panic_halt;
+
+const ADDR: *mut u8 = 0x0000_1000 as *mut u8;
+
+fn print(s: &str) {
+    for b in s.bytes() {
+        unsafe {
+            ADDR.write_volatile(b);
+        }
+    }
+}
+
+struct PrintAddr;
+
+impl core::fmt::Write for PrintAddr {
+    fn write_str(&mut self, s: &str) -> core::fmt::Result {
+        print(s);
+        Ok(())
+    }
+}
+
+#[cfg_attr(not(test), entry)]
+fn main() -> ! {
+    let mut addr = PrintAddr;
+
+    print("This test makes sure the FPU works as expected\n");
+
+    #[allow(clippy::unnecessary_cast)]
+    let _ = writeln!(addr, "79823i32 as f32 = {}", 79823i32 as f32);
+
+    let _ = writeln!(addr, "1.3 + 5.3 = {}", 1.3f32 + 5.3f32);
+    let _ = writeln!(addr, "5.3 - 1.3 = {}", 5.3f32 - 1.3f32);
+
+    let _ = writeln!(addr, "24.65 * 43.2 = {}", 24.65f32 * 43.2f32);
+
+    let _ = writeln!(addr, "12.6 / 4.2 = {}", 12.6f32 / 4.2f32);
+
+    loop {
+        continue;
+    }
+}