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Test suite: fix topEntity inclusion Ram/RMultiTop #2195

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Jun 14, 2022
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Test suite: fix topEntity inclusion Ram/RMultiTop #2195

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26 changes: 17 additions & 9 deletions tests/shouldwork/Signal/Ram/RMulti.hs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,44 +2,52 @@
--
-- Test reading with a fast clock. Memory is initialized through the write port,
-- but after that the write side is dormant.

{-# OPTIONS_GHC -Wno-orphans #-}

Comment on lines +5 to +7
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This shouldn't be needed.

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@DigitalBrains1 DigitalBrains1 May 18, 2022 •
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Depends on your definition of "needed". I like to compile HDL with -Wall and not have any warnings, and then it's needed, since we use createDomain below.

So instead of "this shouldn't be needed", I'd like to counter "we should change CI so this actually is needed" 😆

(I'm not actually suggesting we do that now)

module RMulti where

import Clash.Explicit.Prelude
import Clash.Explicit.Testbench
import qualified Prelude as P

createDomain vSystem{vName="P10", vPeriod=10000}
createDomain vSystem{vName="P20", vPeriod=20000}

ram
:: Clock P20
type Ram =
Clock P20
-> Clock P10
-> Signal P10 (Unsigned 1)
-> Signal P20 (Maybe (Unsigned 1, Unsigned 2))
-> Signal P10 (Unsigned 2)

ram
:: Ram
ram wClk rClk = asyncRamPow2 wClk rClk enableGen

tbOutput
:: Clock P20
:: Ram
-> Clock P20
-> Clock P10
-> Signal P10 (Unsigned 2)
tbOutput wClk rClk = output
tbOutput top wClk rClk = output
where
wrM = stimuliGenerator wClk wNoReset $
Just (0, 1) :> Just (1,2) :> Nothing :> Nil
rd = delay rClk enableGen 0 $ rd + 1
output = ignoreFor rClk rNoReset enableGen d2 0 $ ram wClk rClk rd wrM
output = ignoreFor rClk rNoReset enableGen d2 0 $ top wClk rClk rd wrM
wNoReset = unsafeFromHighPolarity @P20 (pure False)
rNoReset = unsafeFromHighPolarity @P10 (pure False)
{-# INLINE tbOutput #-}

tb
:: ( KnownNat n
, 1 <= n)
=> Vec n (Unsigned 2)
=> Ram
-> Vec n (Unsigned 2)
-> Signal P10 Bool
tb expectedSamples = done
tb top expectedSamples = done
where
output = tbOutput wClk rClk
output = tbOutput top wClk rClk
expectedOutput = outputVerifier' rClk noReset expectedSamples
done = expectedOutput output
(rClk, wClk) = biTbClockGen (not <$> done) :: (Clock P10, Clock P20)
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3 changes: 2 additions & 1 deletion tests/shouldwork/Signal/Ram/RMultiTop.hs
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Expand Up @@ -15,5 +15,6 @@ topEntity = ram

testBench
:: Signal P10 Bool
testBench = tb $(listToVecTH $ sampleN 20 $ tbOutput clockGen clockGen)
testBench = tb topEntity
$(listToVecTH $ sampleN 20 $ tbOutput ram clockGen clockGen)
{-# NOINLINE testBench #-}