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verilog-language-server_test: Added register variable and gate symbol…
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…s test

Signed-off-by: Jan Bylicki <[email protected]>
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jbylicki committed Jun 16, 2023
1 parent 5ff1475 commit b4e9fbf
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Showing 2 changed files with 17 additions and 3 deletions.
4 changes: 2 additions & 2 deletions verilog/tools/ls/document-symbol-filler.cc
Original file line number Diff line number Diff line change
Expand Up @@ -107,7 +107,7 @@ void DocumentSymbolFiller::Visit(const verible::SyntaxTreeNode &node) {
break;
}
case verilog::NodeEnum::kRegisterVariable: {
const auto* variable_name =
const auto *variable_name =
GetSubtreeAsLeaf(node, NodeEnum::kRegisterVariable, 0);
if (variable_name) {
is_visible_node = true;
Expand All @@ -118,7 +118,7 @@ void DocumentSymbolFiller::Visit(const verible::SyntaxTreeNode &node) {
break;
}
case verilog::NodeEnum::kGateInstance: {
const auto* variable_name =
const auto *variable_name =
GetSubtreeAsLeaf(node, NodeEnum::kGateInstance, 0);
if (variable_name) {
is_visible_node = true;
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16 changes: 15 additions & 1 deletion verilog/tools/ls/verilog-language-server_test.cc
Original file line number Diff line number Diff line change
Expand Up @@ -284,6 +284,11 @@ endpackage
module mini(input clk);
always@(posedge clk) begin : labelled_block
end
reg foo;
net bar;
some_class baz();
endmodule
)");

Expand Down Expand Up @@ -331,9 +336,18 @@ endmodule

// Descent tree into module and find labelled block.
std::vector<verible::lsp::DocumentSymbol> module = toplevel[1].children;
EXPECT_EQ(module.size(), 1);
EXPECT_EQ(module.size(), 4);
EXPECT_EQ(module[0].kind, verible::lsp::SymbolKind::kNamespace);
EXPECT_EQ(module[0].name, "labelled_block");

EXPECT_EQ(module[1].kind, verible::lsp::SymbolKind::kVariable);
EXPECT_EQ(module[1].name, "foo");

EXPECT_EQ(module[2].kind, verible::lsp::SymbolKind::kVariable);
EXPECT_EQ(module[2].name, "bar");

EXPECT_EQ(module[3].kind, verible::lsp::SymbolKind::kVariable);
EXPECT_EQ(module[3].name, "baz");
}

// Tests closing of the file in the LS context and checks if the LS
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