Merge pull request #2234 from aavdiere/master

[LINT] Add interconnect unit test, PR #2188
chipsalliance · Sep 17, 2024 · 9f80442 · 9f80442
2 parents e575e51 + 629774e
commit 9f80442
Showing 1 changed file with 3 additions and 2 deletions.
diff --git a/verilog/parser/verilog_parser_unittest.cc b/verilog/parser/verilog_parser_unittest.cc
@@ -3500,8 +3500,9 @@ static constexpr ParserTestCaseArray kModuleTests = {
 
 static constexpr ParserTestCaseArray kModuleInstanceTests = {
     "module tryme;\n"
-    "logic lol;\n"   // is a data_declaration
-    "wire money;\n"  // is a net_declaration
+    "logic lol;\n"           // is a data_declaration
+    "wire money;\n"          // is a net_declaration
+    "interconnect floyd;\n"  // is a TK_interconnect
     "endmodule",
     "module tryme;\n"
     "foo a;\n"  // looks like data_declaration