verilog: parser: verilog.y: Fixed creation of DataTypes for net_variable

Signed-off-by: Grzegorz Latosinski <[email protected]>
chipsalliance · Jun 16, 2023 · 4357fbb · 4357fbb
1 parent 5af3b60
commit 4357fbb
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/verilog/parser/verilog.y b/verilog/parser/verilog.y
@@ -5572,11 +5572,11 @@ net_declaration
   //   trailing_assign_opt ',' net_decl_assigns ';'
   // | net_type data_type_or_implicit drive_strength net_decl_assigns ';'
   | TK_trireg charge_strength_opt decl_dimensions_opt delay3_opt list_of_identifiers ';'
-    { $$ = MakeTaggedNode(N::kNetDeclaration, MakeDataType($1), $2,
+    { $$ = MakeTaggedNode(N::kNetDeclaration, MakeDataType(nullptr, $1, $4, nullptr), $2,
                           MakePackedDimensionsNode($3),
-                          $4, $5, $6); }
+                          $5, $6); }
   | net_type delay3 net_variable_or_decl_assigns ';'
-  { $$ = MakeTaggedNode(N::kNetDeclaration, MakeDataType($1), nullptr, nullptr, $2, $3, $4); }
+  { $$ = MakeTaggedNode(N::kNetDeclaration, MakeDataType(nullptr, $1, $2, nullptr), nullptr, nullptr, $3, $4); }
   /* TODO(fangism): net_type_identifer [ delay_control ] list_of_net_decl_assignments */
   /* TODO(fangism): TK_interconnect ... */
   ;