IP Emulator should set CSR for performance evaulation.

[sequencer]

IP Emulator is designed for simulate vector instructions w/o a scalar core, thus we use spike as scalar core. For now, each vector commits only used for cosim, and won't change the state of scalar core.

If we want to do some performance benchmark with ip emulator, we should set mcycle with simulation cycles.

This is not grantee to be accurate for program performance, but should be fine for an intensive vectorized workload.

In the future, we should also think about adding Zihpm support for T1, here is the roadmap:

• Start to perf with chisel Probe API, it will be lowered to Verilog XMR, without adding hardware overhead to RTL.
• Sort out all important events we need to care about, schedule hpm counter for these events.
• Change these Probe to a real hardware IO, and maintain performance counter on the Sequencer.
• Expose these CSR(maybe hardwired) to scalar CSR Module(we also need to refactor RocketCSR).