Merge pull request #3694 from ngc7331/upstream/fix-rvc-caddi4spn-ill

Fix: c.addi4spn with imm=0 and rd'!=0 should be reserved
chipsalliance · Jan 28, 2025 · 8fa6290 · 8fa6290
2 parents ea7bb3a + b5f5a8e
commit 8fa6290
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/rocket/RVC.scala b/src/main/scala/rocket/RVC.scala
@@ -155,12 +155,12 @@ class RVCDecoder(x: UInt, xLen: Int, fLen: Int, useAddiForMv: Boolean = false) {
   }
 
   def q0_ill = {
-    def allz = !(x(12, 2).orR)
+    def immz = !(x(12, 5).orR)
     def fld = if (fLen >= 64) false.B else true.B
     def flw32 = if (xLen == 64 || fLen >= 32) false.B else true.B
     def fsd = if (fLen >= 64) false.B else true.B
     def fsw32 = if (xLen == 64 || fLen >= 32) false.B else true.B
-    Seq(allz, fld, false.B, flw32, true.B, fsd, false.B, fsw32)
+    Seq(immz, fld, false.B, flw32, true.B, fsd, false.B, fsw32)
   }
 
   def q1_ill = {