This repository hosts unit tests generator for the RISC-V vector extension.
- Similar to riscv-tests, simple and easy to use
- Self-verification by default, Co-simulator friendly
- User-mode and machine-mode binaries
- TestFloat3 integration
- Support RV32 and RV64
- Test SEW from e8 to e64
- Test LMUL from mf8 to m8
- Support VLEN from 64 to 4096
- Support varies sub-extensions: Zvfh, Zvbb, Zvbc, Zvkg, Zvkned, Zvknha, Zvksed and Zvksh
- Configurable, see
make help
- All the tests are per instruction, and it is done more or less in the same fashion
- Lack of tail/mask agnostic support (i.e. ta/ma)
- Lack of fault-only-first testing
- Lack of vstart testing
- Lack of register group overlap testing
- ... and more
Overall, there are no coverage statistics or guarantees.
The Spike simulator is known as the RISC-V gold standard simulator, and although we don't know how Spike is tested, it does fully support the V extension. So we added a custom special instruction to Spike, and for any test, let it automatically generate a reference result for that test. This way, we generate tests for all instructions almost automatically. Under this framework, all we have to do is write a simple config file for each instruction.
riscv64-unknown-elf-gcc
with RVV 1.0 support- The Spike simulator
- Golang 1.19+
riscv-pk
if you need to generate user-mode binaries
make all -j$(nproc)
If you have problems compiling, please refer to the build steps in build-and-test.yml.
After make all
, you will find all the generated tests in out/v[vlen]x[xlen][mode]/bin/stage2/
.
For more advanced options, run make help
.
Note: single/single.go generates tests directly from stage 1, suitable for targets with co-simulators (or simply use
TEST_MODE=cosim
if you're lazy).
This repository also provides a nix derivation with the following output provided:
${riscv-vector-test}/bin/*
: Generator binaries${riscv-vector-test}/include/*
: Necessary headers for runtime usage${riscv-vector-test}/configs/*
: Necessary runtime configs
This project uses third-party projects, and the licenses of these projects are attached to the corresponding directories.
The code for this project is distributed under the Apache License Version 2.0.
The “RISC-V” trade name is a registered trademark of RISC-V International.