Fix "Type Alias" section location. (#128)

Section "Type Alias" was visibly inserted in the middle of the
"Reference Types" section. This lead to some subsections of "Reference
Types" being attached to the "Type Alias" section.

revision-history.yaml

@@ -6,6 +6,8 @@ revisionHistory:
   thisVersion:
     spec:
       - Add optional groups.
+      - Fix position of "Type Alias" (it used to be in the middle of
+        "Reference Types").
     abi:
       - Add ABI for optional groups.
   # Information about the old versions.  This should be static.

spec.md

@@ -862,32 +862,6 @@ Probe types may target `const`{.firrtl} signals, but cannot use
 `RWProbe<const T>`{.firrtl}, as constant values should never be mutated at
 runtime.
 
-## Type Alias
-
-A type alias is a mechanism to assign names to existing FIRRTL types. Type aliases
-enables their reuse across multiple declarations.
-
-```firrtl
-type WordType = UInt<32>
-type ValidType = UInt<1>
-type Data = {w: WordType, valid: ValidType, flip ready: UInt<1>}
-type AnotherWordType = UInt<32>
-
-module TypeAliasMod:
-  input in: Data
-  output out: Data
-  wire w: AnotherWordType
-  connect w, in.w
-  ...
-```
-
-The `type` declaration is globally defined and all named types exist in the same
-namespace and thus must all have a unique name. Type aliases do not share the same
-namespace as modules; hence it is allowed for type aliases to conflict with module
-names. Note that when we compare two types, the equivalence is determined solely by
-their structures. For instance types of `w`{.firrtl} and `in.w`{.firrtl} are
-equivalent in the example above even though they are different type alias.
-
 #### Width and Reset Inference
 
 Probe types do participate in global width and reset inference, but only in the
@@ -1075,6 +1049,32 @@ module Top:
   node consumer_debug = read(c.out.cref); ; Consumer-side signal
 ```
 
+## Type Alias
+
+A type alias is a mechanism to assign names to existing FIRRTL types. Type aliases
+enables their reuse across multiple declarations.
+
+```firrtl
+type WordType = UInt<32>
+type ValidType = UInt<1>
+type Data = {w: WordType, valid: ValidType, flip ready: UInt<1>}
+type AnotherWordType = UInt<32>
+
+module TypeAliasMod:
+  input in: Data
+  output out: Data
+  wire w: AnotherWordType
+  connect w, in.w
+  ...
+```
+
+The `type` declaration is globally defined and all named types exist in the same
+namespace and thus must all have a unique name. Type aliases do not share the same
+namespace as modules; hence it is allowed for type aliases to conflict with module
+names. Note that when we compare two types, the equivalence is determined solely by
+their structures. For instance types of `w`{.firrtl} and `in.w`{.firrtl} are
+equivalent in the example above even though they are different type alias.
+
 ## Property Types
 
 FIRRTL property types represent information about the circuit that is not