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317 Open 747 Closed
317 Open 747 Closed
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Issues list

SingleTargetAnnotations will report java.lang.NumberFormatException when indexing a Vec chisel type
#4575 opened Dec 24, 2024 by davine47
1
Regarding the loss of active reset behavior of Reg or being overridden by RegInit.
#4567 opened Dec 18, 2024 by linmoIO
3
chisel3.util.Queue not working with SInt bug
#4536 opened Nov 27, 2024 by jiegec
1
3
Semantic Inconsistency in Intermediate FIRRTL File During Compilation: Incorrect reg Emission Instead of node and Loss of Memory readUnderWrite Behavior
#4526 opened Nov 25, 2024 by linmoIO
2
ChiselSim: vcd shows clock=1 for threes consecutive time steps
#4516 opened Nov 19, 2024 by toreba
1
Initialize (FPGA) memory in Chisel 6
#4496 opened Nov 6, 2024 by schoeberl
Need for explicit widths in BlackBox parameters
#4488 opened Oct 26, 2024 by HakamAtassi
Selecting instances when using D/I and Class Property types crashes
#4476 opened Oct 16, 2024 by jackkoenig
1
Layers not emitted when used as colors of probes with separate elaboration
#4469 opened Oct 15, 2024 by dtzSiFive
PriorityMux drops arguments if input sequences are not the same size bug good first issue An issue whose fix is simple. Perfect for a new developer wanting to get involved!
#4444 opened Oct 4, 2024 by jackkoenig
1
SyncReadMem ruw (ReadUnderWrite) parameter has no effect
#4433 opened Oct 2, 2024 by maxbjurling
2
Probe color should be checked for read bug
#4406 opened Sep 19, 2024 by dtzSiFive
Lexical scope is not properly checked for ports of submodules bug
#4405 opened Sep 18, 2024 by jackkoenig
2
Update docs/README.md good first issue An issue whose fix is simple. Perfect for a new developer wanting to get involved!
#4402 opened Sep 16, 2024 by jackkoenig
1
bundleWithABoolProbe := 0.U.asTypeOf(bundleWithABoolProbe) results in illegal firrtl bug
#4388 opened Sep 10, 2024 by mwachs5
Path values do not work with multiple instantiation bug
#4379 opened Sep 3, 2024 by jackkoenig 7.0
Wrong memory initialization with ChiselSim bug
#4340 opened Aug 12, 2024 by rameloni
2
How to access chisel-generated modules using SystemVerilog interface
#4313 opened Jul 26, 2024 by thuako
Scala version
#4293 opened Jul 19, 2024 by schoeberl
3
Firtool error occurs when looking up parameters from a definition of a Module with reset
#4292 opened Jul 19, 2024 by unlsycn
1
Proposal for Verification IR with reset
#4282 opened Jul 17, 2024 by poemonsense
2
SVSim fails when pokeing and incrementing clock in loop
#4281 opened Jul 16, 2024 by HakamAtassi
API for specifying customized transforms in ChiselStage (and dependencies?)
#4280 opened Jul 16, 2024 by poemonsense
1
ChiselSim waveforms
#4246 opened Jul 7, 2024 by HakamAtassi
5
Please make some classes in simulator package public for simulator customization.
#4240 opened Jul 2, 2024 by zhutmost
ProTip! Updated in the last three days: updated:>2024-12-23.