Support boring on original Module after .toInstance call (backport #4602) (#4604)

* Support boring on original Module after .toInstance call (#4602)

(cherry picked from commit 4d162c4)

* Add needed private API and change new test to 6.x-style

---------

Co-authored-by: Jack Koenig <[email protected]>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Author: mergify[bot]

core/src/main/scala/chisel3/Module.scala

@@ -578,6 +578,12 @@ package experimental {
       _ports.toSeq
     }
 
+    /** Get IOs that are currently bound to this module.
+      */
+    private[chisel3] def getIOs: Seq[Data] = {
+      _ports.map(_._1).toSeq
+    }
+
     // These methods allow checking some properties of ports before the module is closed,
     // mainly for compatibility purposes.
     protected def portsContains(elem: Data): Boolean = {

core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala

@@ -352,7 +352,7 @@ object Lookupable {
         def getIoMap(hierarchy: Hierarchy[_]): Option[Map[Data, Data]] = {
           hierarchy.underlying match {
             case Clone(x: ModuleClone[_]) => Some(x.ioMap)
-            case Proto(x: BaseModule) => Some(x.getChiselPorts.map { case (_, data: Data) => data -> data }.toMap)
+            case Proto(x: BaseModule) => Some(x.getIOs.map { data => data -> data }.toMap)
             case Clone(x: InstantiableClone[_]) => getIoMap(x._innerContext)
             case Clone(x: InstanceClone[_]) => None
             case other => {

src/test/scala/chiselTests/BoringUtilsSpec.scala

@@ -320,6 +320,34 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
     log should include("Can only bore into modules that are not fully closed")
   }
 
+  it should "support boring on a Module even after .toInstance (and accessing a port)" in {
+    import chisel3.experimental.hierarchy._
+    @instantiable
+    class Bar extends RawModule {
+      @public val port = IO(Output(UInt(8.W)))
+      val a_wire = WireInit(UInt(1.W), DontCare)
+    }
+    class Foo extends RawModule {
+      val bar = Module(new Bar)
+      val bi = bar.toInstance
+      val x = BoringUtils.bore(bar.a_wire)
+      val p = bi.port // Previously, the lookup here would close the module due to reflecting on the IOs of bar
+      val y = BoringUtils.bore(bar.a_wire)
+    }
+
+    val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Foo)
+    matchesAndOmits(chirrtl)(
+      "module Bar :",
+      "output x_bore : UInt<1>",
+      "output y_bore : UInt<1>",
+      "connect x_bore, a_wire",
+      "connect y_bore, a_wire",
+      "module Foo :",
+      "connect x, bar.x_bore",
+      "connect y, bar.y_bore"
+    )()
+  }
+
   it should "not create a new port when source is a port" in {
     class Baz extends RawModule {
       val a = IO(Output(Bool()))