release_v20231011_1

Switch nightly release to use FPGA tests rather than verilator

For the past few weeks, the nightly verilator suite has executing ALL the
tests, even those that are known to fail against the RTL-based hardware
models.  As it has never passed since this change, there's no need to
have it block the release.

The current FPGA suite (also RTL-based) covers more tests than the
original verilator suite used by the nightly release workflow, so it
should be adequate for now.