Check extended error info in test_rom_wdt_timeout

rom/dev/doc/test-coverage/test-coverage.md

@@ -118,6 +118,7 @@ Check value in WarmResetEntry4::RomUpdateResetStatus datavault register | **test
 Test Scenario| Test Name | ROM Error Code
 ---|---|---
 Check for any RUST panics added to the code | **test_panic_missing** | N/A
+Checks that extended error info is populated correctly upon watchdog timer timeout | **test_rom_wdt_timeout** | ROM_GLOBAL_WDT_EXPIRED
 
 
 # **Test Gaps**
@@ -126,7 +127,6 @@ Test Scenario| Test Name | ROM Error Code
 Expand `smoke_test` to perform a hitless update and confirm everything is mixed into the identity correctly. | N/A | N/A
 Validate fix for #817: warm reset during hitless update | N/A | N/A
 Validate fix for #628: warm reset during cold reset | N/A | N/A
-Add test for watchdog failure, and that extended error info is populated correctly | N/A | N/A
 Add test for CPU fault, and that extended error info is populated correctly | N/A | N/A
 Stress test: Perform many hitless updates in a row | N/A | N/A
 Ensure that boot ROM can load a 128k bundle into ICCM (assert ICCM contents in test) | N/A | N/A

rom/dev/tests/rom_integration_tests/test_wdt_activation_and_stoppage.rs

@@ -107,4 +107,30 @@ fn test_rom_wdt_timeout() {
     .unwrap();
 
     hw.step_until(|m| m.soc_ifc().cptra_fw_error_fatal().read() == WDT_EXPIRED);
+
+    let mcause = hw.soc_ifc().cptra_fw_extended_error_info().at(0).read();
+    let mscause = hw.soc_ifc().cptra_fw_extended_error_info().at(1).read();
+    let mepc = hw.soc_ifc().cptra_fw_extended_error_info().at(2).read();
+    let ra = hw.soc_ifc().cptra_fw_extended_error_info().at(3).read();
+    let error_internal_intr_r = hw.soc_ifc().cptra_fw_extended_error_info().at(4).read();
+
+    println!(
+        "WDT Expiry mcause=0x{:08X} mscause=0x{:08X} mepc=0x{:08X} ra=0x{:08X} error_internal_intr_r={:08X}",
+        mcause,
+        mscause,
+        mepc,
+        ra,
+        error_internal_intr_r,
+    );
+
+    // no mcause if wdt times out
+    assert_eq!(mcause, 0);
+    // no mscause if wdt times out
+    assert_eq!(mscause, 0);
+    // mepc is a memory address so won't be 0
+    assert_ne!(mepc, 0);
+    // return address won't be 0
+    assert_ne!(ra, 0);
+    // error_internal_intr_r must be 0b01000000 since the error_wdt_timer1_timeout_sts bit must be set
+    assert_eq!(error_internal_intr_r, 0b01000000);
 }

sw-emulator/lib/periph/src/soc_reg.rs

@@ -103,8 +103,6 @@ mod constants {
     pub const INTERNAL_FW_UPDATE_RESET_START: u32 = 0x624;
     pub const INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_START: u32 = 0x628;
     pub const INTERNAL_NMI_VECTOR_START: u32 = 0x62c;
-    pub const INTR_BLOCK_START: u32 = 0x800;
-    pub const INTR_BLOCK_SIZE: usize = 28;
 }
 use constants::*;
 
@@ -203,6 +201,19 @@ register_bitfields! [
         LMS_VERIFY OFFSET(0) NUMBITS(1) [],
         RSVD OFFSET(1) NUMBITS(31) [],
     ],
+
+    /// ErrorIntrT
+    ErrorIntrT [
+        ERROR_INTERNAL_STS OFFSET(0) NUMBITS(1) [],
+        ERROR_INV_DEV_STS OFFSET(1) NUMBITS(1) [],
+        ERROR_CMD_FAIL_STS OFFSET(2) NUMBITS(1) [],
+        ERROR_BAD_FUSE_STS OFFSET(3) NUMBITS(1) [],
+        ERROR_ICCM_BLOCKED_STS OFFSET(4) NUMBITS(1) [],
+        ERROR_MBOX_ECC_UNC_STS OFFSET(5) NUMBITS(1) [],
+        ERROR_WDT_TIMER1_TIMEOUT_STS OFFSET(6) NUMBITS(1) [],
+        ERROR_WDT_TIMER2_TIMEOUT_STS OFFSET(7) NUMBITS(1) [],
+        RSVD OFFSET(8) NUMBITS(24) [],
+    ]
 ];
 
 /// SOC Register peripheral
@@ -554,9 +565,29 @@ struct SocRegistersImpl {
     #[register(offset = 0x062c, write_fn = on_write_internal_nmi_vector)]
     internal_nmi_vector: ReadWriteRegister<u32>,
 
-    /// INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES Register
-    #[register_array(offset = 0x0800)]
-    intr_block_rf: [u32; INTR_BLOCK_SIZE / 4],
+    /// GLOBAL_INTR_EN_R Register
+    #[register(offset = 0x0800)]
+    global_intr_en_r: ReadWriteRegister<u32>,
+
+    /// ERROR_INTR_EN_R Register
+    #[register(offset = 0x0804)]
+    error_intr_en_r: ReadWriteRegister<u32>,
+
+    /// NOTIF_INTR_EN_R Register
+    #[register(offset = 0x0808)]
+    notif_intr_en_r: ReadWriteRegister<u32>,
+
+    /// ERROR_GLOBAL_INTR_R Register
+    #[register(offset = 0x080c)]
+    error_global_intr_r: ReadWriteRegister<u32>,
+
+    /// NOTIF_GLOBAL_INTR_R Register
+    #[register(offset = 0x0810)]
+    notif_global_intr_r: ReadWriteRegister<u32>,
+
+    /// ERROR_INTERNAL_INTR_R Register
+    #[register(offset = 0x0814)]
+    error_internal_intr_r: ReadWriteRegister<u32, ErrorIntrT::Register>,
 
     /// Mailbox
     mailbox: MailboxInternal,
@@ -676,7 +707,12 @@ impl SocRegistersImpl {
             internal_fw_update_reset: ReadWriteRegister::new(0),
             internal_fw_update_reset_wait_cycles: ReadWriteRegister::new(5),
             internal_nmi_vector: ReadWriteRegister::new(0),
-            intr_block_rf: [0u32; INTR_BLOCK_SIZE / 4],
+            global_intr_en_r: ReadWriteRegister::new(0),
+            error_intr_en_r: ReadWriteRegister::new(0),
+            notif_intr_en_r: ReadWriteRegister::new(0),
+            error_global_intr_r: ReadWriteRegister::new(0),
+            notif_global_intr_r: ReadWriteRegister::new(0),
+            error_internal_intr_r: ReadWriteRegister::new(0),
             mailbox,
             iccm,
             timer: Timer::new(clock),
@@ -870,6 +906,7 @@ impl SocRegistersImpl {
             Some(self.timer.schedule_action_in(0, TimerAction::UpdateReset));
         Ok(())
     }
+
     fn on_write_internal_nmi_vector(&mut self, size: RvSize, val: RvData) -> Result<(), BusError> {
         if size != RvSize::Word {
             return Err(BusError::StoreAccessFault);
@@ -1030,12 +1067,18 @@ impl SocRegistersImpl {
 
         if self.timer.fired(&mut self.op_wdt_timer1_expired_action) {
             self.cptra_wdt_status.reg.modify(WdtStatus::T1_TIMEOUT::SET);
+            self.error_internal_intr_r
+                .reg
+                .modify(ErrorIntrT::ERROR_WDT_TIMER1_TIMEOUT_STS::SET);
 
             // If WDT2 is disabled, schedule a callback on it's expiry.
             if !self.cptra_wdt_timer2_en.reg.is_set(WdtEnable::TIMER_EN) {
                 self.cptra_wdt_status
                     .reg
                     .modify(WdtStatus::T2_TIMEOUT::CLEAR);
+                self.error_internal_intr_r
+                    .reg
+                    .modify(ErrorIntrT::ERROR_WDT_TIMER2_TIMEOUT_STS::CLEAR);
 
                 let timer_period: u64 = (self.cptra_wdt_timer2_timeout_period[1] as u64) << 32
                     | self.cptra_wdt_timer2_timeout_period[0] as u64;
@@ -1050,6 +1093,9 @@ impl SocRegistersImpl {
             // If WDT2 was not scheduled due to WDT1 expiry (i.e WDT2 is disabled), schedule an NMI.
             // Else, do nothing.
             if self.cptra_wdt_timer2_en.reg.is_set(WdtEnable::TIMER_EN) {
+                self.error_internal_intr_r
+                    .reg
+                    .modify(ErrorIntrT::ERROR_WDT_TIMER2_TIMEOUT_STS::SET);
                 return;
             }