Dev msft 20231017 #252
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Dev msft 20231017 #252
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…s at MBOX flow entry Firmware fix to clear any error interrupts held over after previous mailbox flow handling exited, but before the mailbox returned to idle state. Resolves a UVM regression edge case. Also, force firmware randomization seed to match hardware seed by extracting seed value from the yml test file (which accounts for manual override in local runs). Related work items: #565323
Related work items: #565386
Fixing how coverage is merged Related work items: #563789
…o MSFT internal repo MSFT sync: Manual file-copy from GH dev-integrate to MSFT internal repo Related work items: #566127
…age roll up Adding coverage switches to caliptra top directed regression Changes to coverage pipeline to roll up caliptra top directed and random regressions Added symlink to latest merged coverage directory Related work items: #563789
Fix for multi-threaded reg accesses resulting in deadlock on uvm_reg Related work items: #565702
- removing extra pointer resets so that we don't generate spurious interrupts on unnecessary reads of dword 0 - fixing tests added to directed test list, bad path Related work items: #567016
…_unlock deadlock issue Fixes two issues: - Known UVM bug (described here: https://forums.accellera.org/topic/7037-register-write-clobbers-simultaneous-access-in-multi-threaded-testbench/) that causes uvm_reg arbitration to fail (access semaphore has a bug). This causes failures during the multi-agent sequence when multiple agents are trying to access mbox_datain. Solved with an additional application-layer semaphore custom to our reg-block. - A recent fix to solve an unreturned semaphore in the register layer (unrelated to the above) added a bug that may cause deadlock in the error injection CPTRA-side handler sequence when an error occurs. Related work items: #566556, #567666
Randomized timeout values can be small enough that timer1 times out a second time before NMI testing is done in RT. The intr check helps but needs to happen just before the timer is restarted. Related work items: #566167
…ures related to timeouts or Mailbox FSM edge cases When an illegal transfer occurs concurrent with a legal mailbox interaction, the erroneous access should take precedence and flag a protocol violation instead of continuing with the normal flow. * Bug issue: https://dev.azure.com/ms-tsd/AHA_POC/_workitems/edit/519733 * Will not fix for 1p0. Instead, this PR adds an explicit print message when the known failure scenario occurs, to aid regression review. Add a fix for a UVM sequence-specific failure where double-bit ECC error injection can result in a timeout (by corrupting the "expected" response dlen value to a large number). Related work items: #568733, #568736
… [UVM] validation fw fix for error intr handling RTL fix: - Add reset value for mbox_rd_valid_f, resolving a potential issue with mbox_dataout containing X values (resolves #250) UVM Validation fix: - Clear cmd_fail/inv_dev error interrupts at Mbox flow entry (val runtime firmware) Related work items: #569091, #569460
Add - firmware regression list description - enhance UVM run steps - describe test list selection - describe Verilog file list generation and usage
Nitsirks
approved these changes
Oct 20, 2023
bharatpillilli
approved these changes
Oct 20, 2023
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