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[LINT] Resolving unnamed generate blocks Lint warnings (#510)
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* Resolving unnamed generate blocks Lint warnings

* Running stamp_repo.sh

---------

Co-authored-by: Avirup Mullick <[email protected]>
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@amullick007
amullick007 and Avirup Mullick authored May 3, 2024
1 parent 56b2ade commit a070e1d
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Showing 12 changed files with 32 additions and 30 deletions.
2 changes: 1 addition & 1 deletion .github/workflow_metadata/pr_hash
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b6a76c62fb59087fd27c838bf609afbad5b318521c2f9f16d27599ca166e71a67227e054bbfad47824c3c7f09bb4cce7
7ae197dad73f301cd44963a5b43157c795b1b9746051fd526e9e5b9a2257b7e55e4fb7307fb2282317fa475a88cb8af9
2 changes: 1 addition & 1 deletion .github/workflow_metadata/pr_timestamp
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1714443225
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2 changes: 1 addition & 1 deletion src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv
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Expand Up @@ -480,7 +480,7 @@ if(pt.BTB_ENABLE==1) begin
assign dec_i0_predict_p_d.way = dec_i0_brp.way;


if(pt.BTB_FULLYA) begin
if(pt.BTB_FULLYA) begin : genblock
logic btb_error_found, btb_error_found_f;
logic [$clog2(pt.BTB_SIZE)-1:0] fa_error_index_ns;

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12 changes: 7 additions & 5 deletions src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv
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Expand Up @@ -1814,7 +1814,7 @@ end
rvdffe #(32) dicad0h_ff (.*, .en(wr_dicad0h_r | ifu_ic_debug_rd_data_valid), .din(dicad0h_ns[31:0]), .dout(dicad0h[31:0]));


if (pt.ICACHE_ECC == 1) begin
if (pt.ICACHE_ECC == 1) begin : genblock1
// ----------------------------------------------------------------------
// DICAD1 (R/W) (Only accessible in debug mode)
// [6:0] : ECC
Expand All @@ -1829,7 +1829,7 @@ if (pt.ICACHE_ECC == 1) begin
assign dicad1[31:0] = {25'b0, dicad1_raw[6:0]};

end
else begin
else begin : genblock1
// ----------------------------------------------------------------------
// DICAD1 (R/W) (Only accessible in debug mode)
// [3:0] : Parity
Expand Down Expand Up @@ -2160,7 +2160,7 @@ else
end


if(pt.FAST_INTERRUPT_REDIRECT)
if(pt.FAST_INTERRUPT_REDIRECT) begin : genblock2
rvdffie #(31) mstatus_ff (.*, .clk(free_l2clk),
.din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r,
take_ext_int_start, take_ext_int_start_d1, take_ext_int_start_d2, ext_int_freeze,
Expand All @@ -2175,7 +2175,8 @@ else
mhpmc_inc_r_d1[3:0], perfcnt_halted_d1,
mstatus[1:0]}));

else
end
else begin : genblock2
rvdffie #(27) mstatus_ff (.*, .clk(free_l2clk),
.din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r,
mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in,
Expand All @@ -2187,7 +2188,8 @@ else
fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f,
mhpmc_inc_r_d1[3:0], perfcnt_halted_d1,
mstatus[1:0]}));

end

assign perfcnt_halted = ((dec_tlu_dbg_halted & dcsr[DCSR_STOPC]) | dec_tlu_pmu_fw_halted);
assign perfcnt_during_sleep[3:0] = {4{~(dec_tlu_dbg_halted & dcsr[DCSR_STOPC])}} & {mhpme_vec[3][9],mhpme_vec[2][9],mhpme_vec[1][9],mhpme_vec[0][9]};

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2 changes: 1 addition & 1 deletion src/riscv_core/veer_el2/rtl/dec/el2_dec_trigger.sv
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Expand Up @@ -37,7 +37,7 @@ import el2_pkg::*;
logic [3:0][31:0] dec_i0_match_data;
logic [3:0] dec_i0_trigger_data_match;

for (genvar i=0; i<4; i++) begin
for (genvar i=0; i<4; i++) begin : genblock
assign dec_i0_match_data[i][31:0] = ({32{~trigger_pkt_any[i].select & trigger_pkt_any[i].execute}} & {dec_i0_pc_d[31:1], trigger_pkt_any[i].tdata2[0]}); // select=0; do a PC match

rvmaskandmatch trigger_i0_match (.mask(trigger_pkt_any[i].tdata2[31:0]), .data(dec_i0_match_data[i][31:0]), .masken(trigger_pkt_any[i].match), .match(dec_i0_trigger_data_match[i]));
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10 changes: 5 additions & 5 deletions src/riscv_core/veer_el2/rtl/exu/el2_exu_div_ctl.sv
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Expand Up @@ -43,7 +43,7 @@ import el2_pkg::*;


if (pt.DIV_NEW == 0)
begin
begin : genblock1
el2_exu_div_existing_1bit_cheapshortq i_existing_1bit_div_cheapshortq (
.clk ( clk ), // I
.rst_l ( rst_l ), // I
Expand All @@ -60,7 +60,7 @@ import el2_pkg::*;


if ( (pt.DIV_NEW == 1) & (pt.DIV_BIT == 1) )
begin
begin : genblock2
el2_exu_div_new_1bit_fullshortq i_new_1bit_div_fullshortq (
.clk ( clk ), // I
.rst_l ( rst_l ), // I
Expand All @@ -77,7 +77,7 @@ import el2_pkg::*;


if ( (pt.DIV_NEW == 1) & (pt.DIV_BIT == 2) )
begin
begin : genblock3
el2_exu_div_new_2bit_fullshortq i_new_2bit_div_fullshortq (
.clk ( clk ), // I
.rst_l ( rst_l ), // I
Expand All @@ -94,7 +94,7 @@ import el2_pkg::*;


if ( (pt.DIV_NEW == 1) & (pt.DIV_BIT == 3) )
begin
begin : genblock4
el2_exu_div_new_3bit_fullshortq i_new_3bit_div_fullshortq (
.clk ( clk ), // I
.rst_l ( rst_l ), // I
Expand All @@ -111,7 +111,7 @@ import el2_pkg::*;


if ( (pt.DIV_NEW == 1) & (pt.DIV_BIT == 4) )
begin
begin : genblock5
el2_exu_div_new_4bit_fullshortq i_new_4bit_div_fullshortq (
.clk ( clk ), // I
.rst_l ( rst_l ), // I
Expand Down
8 changes: 4 additions & 4 deletions src/riscv_core/veer_el2/rtl/ifu/el2_ifu_aln_ctl.sv
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Expand Up @@ -215,15 +215,15 @@ import el2_pkg::*;
.dout({error_stall, f2val[1:0], f1val[1:0], f0val[1:0] })
);

if(pt.BTB_ENABLE==1) begin
if(pt.BTB_ENABLE==1) begin : genblock1
rvdffe #(BRDATA_SIZE) brdata2ff (.*, .clk(clk), .en(qwen[2]), .din(brdata_in[BRDATA_SIZE-1:0]), .dout(brdata2[BRDATA_SIZE-1:0]));
rvdffe #(BRDATA_SIZE) brdata1ff (.*, .clk(clk), .en(qwen[1]), .din(brdata_in[BRDATA_SIZE-1:0]), .dout(brdata1[BRDATA_SIZE-1:0]));
rvdffe #(BRDATA_SIZE) brdata0ff (.*, .clk(clk), .en(qwen[0]), .din(brdata_in[BRDATA_SIZE-1:0]), .dout(brdata0[BRDATA_SIZE-1:0]));
rvdffe #(MSIZE) misc2ff (.*, .clk(clk), .en(qwen[2]), .din(misc_data_in[MHI:0]), .dout(misc2[MHI:0]));
rvdffe #(MSIZE) misc1ff (.*, .clk(clk), .en(qwen[1]), .din(misc_data_in[MHI:0]), .dout(misc1[MHI:0]));
rvdffe #(MSIZE) misc0ff (.*, .clk(clk), .en(qwen[0]), .din(misc_data_in[MHI:0]), .dout(misc0[MHI:0]));
end
else begin
else begin : genblock1

rvdffie #((MSIZE*3)+(BRDATA_SIZE*3)) miscff (.*,
.din({qwen[2] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc2[MHI:0], brdata2[BRDATA_SIZE-1:0]},
Expand Down Expand Up @@ -573,7 +573,7 @@ end
assign ifu_i0_instr[31:0] = ({32{first4B & alignval[1]}} & ifirst[31:0]) |
({32{first2B & alignval[0]}} & uncompress0[31:0]);

if(pt.BTB_ENABLE==1) begin
if(pt.BTB_ENABLE==1) begin : genblock2

// if you detect br does not start on instruction boundary

Expand All @@ -593,7 +593,7 @@ if(pt.BTB_ENABLE==1) begin
el2_btb_tag_hash_fold #(.pt(pt)) second_brhash(.pc(secondpc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),
.hash(secondbrtag_hash[pt.BTB_BTAG_SIZE-1:0]));
end
else begin
else begin : btbfold
el2_btb_tag_hash #(.pt(pt)) first_brhash (.pc(firstpc [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),
.hash(firstbrtag_hash [pt.BTB_BTAG_SIZE-1:0]));
el2_btb_tag_hash #(.pt(pt)) second_brhash(.pc(secondpc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),
Expand Down
4 changes: 2 additions & 2 deletions src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv
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Expand Up @@ -246,7 +246,7 @@ import el2_pkg::*;

logic exu_flush_final_d1;

if(!pt.BTB_FULLYA) begin
if(!pt.BTB_FULLYA) begin : genblock1
assign fetch_mp_collision_f = ( (exu_mp_btag[pt.BTB_BTAG_SIZE-1:0] == fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]) &
exu_mp_valid & ifc_fetch_req_f &
(exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO])
Expand Down Expand Up @@ -591,7 +591,7 @@ assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);
el2_btb_tag_hash_fold #(.pt(pt)) rdtagp1f(.hash(fetch_rd_tag_p1_f[pt.BTB_BTAG_SIZE-1:0]),
.pc({fetch_addr_p1_f[ pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]}));
end
else begin
else begin : btbfold
el2_btb_tag_hash #(.pt(pt)) rdtagf(.hash(fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]),
.pc({ifc_fetch_addr_f[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]}));
el2_btb_tag_hash #(.pt(pt)) rdtagp1f(.hash(fetch_rd_tag_p1_f[pt.BTB_BTAG_SIZE-1:0]),
Expand Down
4 changes: 2 additions & 2 deletions src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv
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Expand Up @@ -101,7 +101,7 @@ import el2_pkg::*;
// - Miss *or* flush during WFM (icache miss buffer is blocking)
// - Sequential

if(pt.BTB_ENABLE==1) begin
if(pt.BTB_ENABLE==1) begin : genblock1
logic sel_btb_addr_bf;

assign sel_last_addr_bf = ~exu_flush_final & (~ifc_fetch_req_f | ~ic_hit_f);
Expand Down Expand Up @@ -214,7 +214,7 @@ end
rvdffpcie #(31) faddrf1_ff (.*, .en(fetch_bf_en), .din(fetch_addr_bf[31:1]), .dout(ifc_fetch_addr_f[31:1]));


if (pt.ICCM_ENABLE) begin
if (pt.ICCM_ENABLE) begin : genblock2
logic iccm_acc_in_region_bf;
logic iccm_acc_in_range_bf;
rvrangecheck #( .CCM_SADR (pt.ICCM_SADR),
Expand Down
12 changes: 6 additions & 6 deletions src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
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Expand Up @@ -77,10 +77,10 @@ module rvdffsc #( parameter WIDTH=1, SHORT=0 )
);

logic [WIDTH-1:0] din_new;
if (SHORT == 1) begin
if (SHORT == 1) begin : genblock
assign dout = din;
end
else begin
else begin : genblock
assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]);
rvdff #(WIDTH) dffsc (.din(din_new[WIDTH-1:0]), .*);
end
Expand All @@ -98,10 +98,10 @@ module rvdff_fpga #( parameter WIDTH=1, SHORT=0 )
output logic [WIDTH-1:0] dout
);

if (SHORT == 1) begin
if (SHORT == 1) begin : genblock
assign dout = din;
end
else begin
else begin : genblock
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken), .*);
`else
Expand Down Expand Up @@ -151,10 +151,10 @@ module rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 )
);

logic [WIDTH-1:0] din_new;
if (SHORT == 1) begin
if (SHORT == 1) begin : genblock
assign dout = din;
end
else begin
else begin : genblock
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .din(din[WIDTH-1:0] & {WIDTH{~clear}}),.en((en | clear) & clken), .*);
`else
Expand Down
2 changes: 1 addition & 1 deletion src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -623,7 +623,7 @@ import el2_pkg::*;
//------------------------------------------------------------------------------
// Buffer logic
//------------------------------------------------------------------------------
for (genvar i=0; i<DEPTH; i++) begin
for (genvar i=0; i<DEPTH; i++) begin : genblock

assign ibuf_drainvec_vld[i] = (ibuf_drain_vld & (i == ibuf_tag));
assign buf_byteen_in[i] = ibuf_drainvec_vld[i] ? ibuf_byteen_out[3:0] : ((ibuf_byp & ldst_dual_r & (i == WrPtr1_r)) ? ldst_byteen_hi_r[3:0] : ldst_byteen_lo_r[3:0]);
Expand Down
2 changes: 1 addition & 1 deletion src/riscv_core/veer_el2/rtl/lsu/el2_lsu_trigger.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ import el2_pkg::*;
assign ldst_addr_trigger_m[31:0] = lsu_addr_m[31:0] & {32{trigger_enable}};


for (genvar i=0; i<4; i++) begin
for (genvar i=0; i<4; i++) begin : genblock
assign lsu_match_data[i][31:0] = ({32{~trigger_pkt_any[i].select}} & ldst_addr_trigger_m[31:0]) |
({32{trigger_pkt_any[i].select & trigger_pkt_any[i].store}} & store_data_trigger_m[31:0]);

Expand Down

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