[MISC] Regr test updates; soc_ifc cov script; SHA ACC ID convert to U…

…SER; ABR subm update; VeeR update (#649)

* Fix SHA ACC refs to AXI ID -> AXI USER; add coverpoint gen script and update soc_ifc_cov_if

* Update abr submodule

* Update abr submodule

* Fix yml file to point to right test name

* Add smoke_test_kv_mldsa to nightly directed regression

* Add payload_available and image_activated to axi_dma_reg (status0 reg)

* Port connection and signal naming fix

* Intercept latest RV core updates from VeeR repo

* MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-cov-if-gen' with updated timestamp and hash after successful run

---------

Co-authored-by: Kiran Upadhyayula <[email protected]>

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-b6ec230dfa7a26af9d7afc9566ae35622d609f78924b5a1cf4a952192baf6b86da8803708136956fb9aaac5903a643a4
+0295d4a4cf455a21bb80e7ee198b58ffa73f63d8f33810f6f21a542d8c59e56515d728ab2d8041d6cef9fb2a9dedd80f

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1732148023
+1732159831

src/axi/rtl/axi_dma_ctrl.sv

@@ -33,6 +33,7 @@ import soc_ifc_pkg::*;
     // Should only assert when a full block_size of data is available at the
     // recovery interface FIFO
     input logic recovery_data_avail,
+    input logic recovery_image_activated,
 
     // Internal Signaling
     input logic mbox_lock,
@@ -254,12 +255,14 @@ import soc_ifc_pkg::*;
     always_comb hwif_in.ctrl.go.hwclr    = (ctrl_fsm_ps == DMA_DONE) || ((ctrl_fsm_ps == DMA_ERROR) && hwif_out.ctrl.flush.value);
     always_comb hwif_in.ctrl.flush.hwclr = (ctrl_fsm_ps == DMA_IDLE);
 
-    always_comb hwif_in.cap.fifo_max_depth.next      = FIFO_BC/BC;
-    always_comb hwif_in.status0.busy.next            = (ctrl_fsm_ps != DMA_IDLE);
-    always_comb hwif_in.status0.error.next           = (ctrl_fsm_ps == DMA_ERROR);
-    always_comb hwif_in.status0.fifo_depth.next      = 12'(fifo_depth);
-    always_comb hwif_in.status0.axi_dma_fsm_ps.next  = ctrl_fsm_ps;
-    always_comb hwif_in.status1.bytes_remaining.next = bytes_remaining;
+    always_comb hwif_in.cap.fifo_max_depth.next        = FIFO_BC/BC;
+    always_comb hwif_in.status0.busy.next              = (ctrl_fsm_ps != DMA_IDLE);
+    always_comb hwif_in.status0.error.next             = (ctrl_fsm_ps == DMA_ERROR);
+    always_comb hwif_in.status0.fifo_depth.next        = 12'(fifo_depth);
+    always_comb hwif_in.status0.axi_dma_fsm_ps.next    = ctrl_fsm_ps;
+    always_comb hwif_in.status0.payload_available.next = recovery_data_avail;
+    always_comb hwif_in.status0.image_activated.next   = recovery_image_activated;
+    always_comb hwif_in.status1.bytes_remaining.next   = bytes_remaining;
 
 
     // --------------------------------------- //

src/axi/rtl/axi_dma_reg.rdl

@@ -130,7 +130,18 @@ addrmap axi_dma_reg {
             };
             sw=r; hw=rw; encode = axi_dma_fsm_e;
         } axi_dma_fsm_ps[2] = 0;
-        field { desc="RESERVED."; sw=r; } rsvd1[14]=14'h0000;
+        field { desc="Payload Available. Signal indicates data is available.
+                      When the DMA is active and was armed with nonzero block
+                      size, this is used by the hardware to automatically
+                      trigger AXI transactions of the specified block
+                      size, until the total byte count is transferred.";
+                sw=r; hw=w;
+        } payload_available;
+        field { desc="Image Activated. Signal indicates image activation status
+                      reported by Recovery Interface (from Caliptra Subsystem).";
+                sw=r; hw=w;
+        } image_activated;
+        field { desc="RESERVED."; sw=r; } rsvd1[12]=12'h000;
     } status0;
 
     // Status 1

src/axi/rtl/axi_dma_reg.sv

@@ -2967,7 +2967,9 @@ module axi_dma_reg (
     assign readback_array[3][3:2] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? 2'h0 : '0;
     assign readback_array[3][15:4] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? hwif_in.status0.fifo_depth.next : '0;
     assign readback_array[3][17:16] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? field_storage.status0.axi_dma_fsm_ps.value : '0;
-    assign readback_array[3][31:18] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? 14'h0 : '0;
+    assign readback_array[3][18:18] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? hwif_in.status0.payload_available.next : '0;
+    assign readback_array[3][19:19] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? hwif_in.status0.image_activated.next : '0;
+    assign readback_array[3][31:20] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? 12'h0 : '0;
     assign readback_array[4][31:0] = (decoded_reg_strb.status1 && !decoded_req_is_wr) ? hwif_in.status1.bytes_remaining.next : '0;
     assign readback_array[5][31:0] = (decoded_reg_strb.src_addr_l && !decoded_req_is_wr) ? field_storage.src_addr_l.addr_l.value : '0;
     assign readback_array[6][31:0] = (decoded_reg_strb.src_addr_h && !decoded_req_is_wr) ? field_storage.src_addr_h.addr_h.value : '0;

src/axi/rtl/axi_dma_reg_pkg.sv

@@ -43,11 +43,21 @@ package axi_dma_reg_pkg;
         logic [1:0] next;
     } axi_dma_reg__status0__axi_dma_fsm_ps__in_t;
 
+    typedef struct packed{
+        logic next;
+    } axi_dma_reg__status0__payload_available__in_t;
+
+    typedef struct packed{
+        logic next;
+    } axi_dma_reg__status0__image_activated__in_t;
+
     typedef struct packed{
         axi_dma_reg__status0__busy__in_t busy;
         axi_dma_reg__status0__error__in_t error;
         axi_dma_reg__status0__fifo_depth__in_t fifo_depth;
         axi_dma_reg__status0__axi_dma_fsm_ps__in_t axi_dma_fsm_ps;
+        axi_dma_reg__status0__payload_available__in_t payload_available;
+        axi_dma_reg__status0__image_activated__in_t image_activated;
     } axi_dma_reg__status0__in_t;
 
     typedef struct packed{

src/axi/rtl/axi_dma_reg_uvm.sv

@@ -160,13 +160,17 @@ package axi_dma_reg_uvm;
         axi_dma_reg__status0_bit_cg rsvd0_bit_cg[2];
         axi_dma_reg__status0_bit_cg fifo_depth_bit_cg[12];
         axi_dma_reg__status0_bit_cg axi_dma_fsm_ps_bit_cg[2];
-        axi_dma_reg__status0_bit_cg rsvd1_bit_cg[14];
+        axi_dma_reg__status0_bit_cg payload_available_bit_cg[1];
+        axi_dma_reg__status0_bit_cg image_activated_bit_cg[1];
+        axi_dma_reg__status0_bit_cg rsvd1_bit_cg[12];
         axi_dma_reg__status0_fld_cg fld_cg;
         rand uvm_reg_field busy;
         rand uvm_reg_field error;
         rand uvm_reg_field rsvd0;
         rand uvm_reg_field fifo_depth;
         rand uvm_reg_field axi_dma_fsm_ps;
+        rand uvm_reg_field payload_available;
+        rand uvm_reg_field image_activated;
         rand uvm_reg_field rsvd1;
 
         function new(string name = "axi_dma_reg__status0");
@@ -189,14 +193,20 @@ package axi_dma_reg_uvm;
             this.fifo_depth.configure(this, 12, 4, "RO", 1, 'h0, 0, 1, 0);
             this.axi_dma_fsm_ps = new("axi_dma_fsm_ps");
             this.axi_dma_fsm_ps.configure(this, 2, 16, "RO", 1, 'h0, 1, 1, 0);
+            this.payload_available = new("payload_available");
+            this.payload_available.configure(this, 1, 18, "RO", 1, 'h0, 0, 1, 0);
+            this.image_activated = new("image_activated");
+            this.image_activated.configure(this, 1, 19, "RO", 1, 'h0, 0, 1, 0);
             this.rsvd1 = new("rsvd1");
-            this.rsvd1.configure(this, 14, 18, "RO", 0, 'h0, 1, 1, 0);
+            this.rsvd1.configure(this, 12, 20, "RO", 0, 'h0, 1, 1, 0);
             if (has_coverage(UVM_CVR_REG_BITS)) begin
                 foreach(busy_bit_cg[bt]) busy_bit_cg[bt] = new();
                 foreach(error_bit_cg[bt]) error_bit_cg[bt] = new();
                 foreach(rsvd0_bit_cg[bt]) rsvd0_bit_cg[bt] = new();
                 foreach(fifo_depth_bit_cg[bt]) fifo_depth_bit_cg[bt] = new();
                 foreach(axi_dma_fsm_ps_bit_cg[bt]) axi_dma_fsm_ps_bit_cg[bt] = new();
+                foreach(payload_available_bit_cg[bt]) payload_available_bit_cg[bt] = new();
+                foreach(image_activated_bit_cg[bt]) image_activated_bit_cg[bt] = new();
                 foreach(rsvd1_bit_cg[bt]) rsvd1_bit_cg[bt] = new();
             end
             if (has_coverage(UVM_CVR_FIELD_VALS))

src/axi/rtl/axi_dma_top.sv

@@ -36,6 +36,7 @@ import soc_ifc_pkg::*;
     // Should only assert when a full block_size of data is available at the
     // recovery interface FIFO
     input logic recovery_data_avail,
+    input logic recovery_image_activated,
 
     // SOC_IFC Internal Signaling
     input logic mbox_lock,
@@ -104,6 +105,7 @@ import soc_ifc_pkg::*;
         // Should only assert when a full block_size of data is available at the
         // recovery interface FIFO
         .recovery_data_avail(recovery_data_avail),
+        .recovery_image_activated(recovery_image_activated),
 
         // Internal Signaling
         .mbox_lock(mbox_lock),

src/integration/rtl/caliptra_reg.h

@@ -5084,8 +5084,8 @@
 #define SHA512_ACC_CSR_LOCK                                                                         (0x0)
 #define SHA512_ACC_CSR_LOCK_LOCK_LOW                                                                (0)
 #define SHA512_ACC_CSR_LOCK_LOCK_MASK                                                               (0x1)
-#define CLP_SHA512_ACC_CSR_ID                                                                       (0x30021004)
-#define SHA512_ACC_CSR_ID                                                                           (0x4)
+#define CLP_SHA512_ACC_CSR_USER                                                                     (0x30021004)
+#define SHA512_ACC_CSR_USER                                                                         (0x4)
 #define CLP_SHA512_ACC_CSR_MODE                                                                     (0x30021008)
 #define SHA512_ACC_CSR_MODE                                                                         (0x8)
 #define SHA512_ACC_CSR_MODE_MODE_LOW                                                                (0)
@@ -5276,8 +5276,12 @@
 #define AXI_DMA_REG_STATUS0_FIFO_DEPTH_MASK                                                         (0xfff0)
 #define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_LOW                                                      (16)
 #define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_MASK                                                     (0x30000)
-#define AXI_DMA_REG_STATUS0_RSVD1_LOW                                                               (18)
-#define AXI_DMA_REG_STATUS0_RSVD1_MASK                                                              (0xfffc0000)
+#define AXI_DMA_REG_STATUS0_PAYLOAD_AVAILABLE_LOW                                                   (18)
+#define AXI_DMA_REG_STATUS0_PAYLOAD_AVAILABLE_MASK                                                  (0x40000)
+#define AXI_DMA_REG_STATUS0_IMAGE_ACTIVATED_LOW                                                     (19)
+#define AXI_DMA_REG_STATUS0_IMAGE_ACTIVATED_MASK                                                    (0x80000)
+#define AXI_DMA_REG_STATUS0_RSVD1_LOW                                                               (20)
+#define AXI_DMA_REG_STATUS0_RSVD1_MASK                                                              (0xfff00000)
 #define CLP_AXI_DMA_REG_STATUS1                                                                     (0x30022010)
 #define AXI_DMA_REG_STATUS1                                                                         (0x10)
 #define CLP_AXI_DMA_REG_SRC_ADDR_L                                                                  (0x30022014)

src/integration/rtl/caliptra_reg_defines.svh

@@ -5084,8 +5084,8 @@
 `define SHA512_ACC_CSR_LOCK                                                                         (32'h0)
 `define SHA512_ACC_CSR_LOCK_LOCK_LOW                                                                (0)
 `define SHA512_ACC_CSR_LOCK_LOCK_MASK                                                               (32'h1)
-`define CLP_SHA512_ACC_CSR_ID                                                                       (32'h30021004)
-`define SHA512_ACC_CSR_ID                                                                           (32'h4)
+`define CLP_SHA512_ACC_CSR_USER                                                                     (32'h30021004)
+`define SHA512_ACC_CSR_USER                                                                         (32'h4)
 `define CLP_SHA512_ACC_CSR_MODE                                                                     (32'h30021008)
 `define SHA512_ACC_CSR_MODE                                                                         (32'h8)
 `define SHA512_ACC_CSR_MODE_MODE_LOW                                                                (0)
@@ -5276,8 +5276,12 @@
 `define AXI_DMA_REG_STATUS0_FIFO_DEPTH_MASK                                                         (32'hfff0)
 `define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_LOW                                                      (16)
 `define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_MASK                                                     (32'h30000)
-`define AXI_DMA_REG_STATUS0_RSVD1_LOW                                                               (18)
-`define AXI_DMA_REG_STATUS0_RSVD1_MASK                                                              (32'hfffc0000)
+`define AXI_DMA_REG_STATUS0_PAYLOAD_AVAILABLE_LOW                                                   (18)
+`define AXI_DMA_REG_STATUS0_PAYLOAD_AVAILABLE_MASK                                                  (32'h40000)
+`define AXI_DMA_REG_STATUS0_IMAGE_ACTIVATED_LOW                                                     (19)
+`define AXI_DMA_REG_STATUS0_IMAGE_ACTIVATED_MASK                                                    (32'h80000)
+`define AXI_DMA_REG_STATUS0_RSVD1_LOW                                                               (20)
+`define AXI_DMA_REG_STATUS0_RSVD1_MASK                                                              (32'hfff00000)
 `define CLP_AXI_DMA_REG_STATUS1                                                                     (32'h30022010)
 `define AXI_DMA_REG_STATUS1                                                                         (32'h10)
 `define CLP_AXI_DMA_REG_SRC_ADDR_L                                                                  (32'h30022014)

src/integration/rtl/caliptra_top.sv

@@ -76,6 +76,7 @@ module caliptra_top
     output logic                       mailbox_flow_done,
 
     input  logic                       recovery_data_avail,
+    input  logic                       recovery_image_activated,
 
     input logic                        BootFSM_BrkPoint,
 
@@ -1202,6 +1203,7 @@ soc_ifc_top1
     .mailbox_flow_done(mailbox_flow_done),
 
     .recovery_data_avail(recovery_data_avail),
+    .recovery_image_activated(recovery_image_activated),
 
     .security_state(cptra_security_state_Latched),
 

src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml

@@ -43,6 +43,7 @@ contents:
 #        - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_sha512_flow/smoke_test_kv_sha512_flow.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_crypto_flow/smoke_test_kv_crypto_flow.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_cg/smoke_test_kv_cg.yml
+        - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_mldsa/smoke_test_kv_mldsa.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_pcr_signing/smoke_test_pcr_signing.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml

src/integration/tb/caliptra_top_tb.sv

@@ -237,6 +237,7 @@ caliptra_top caliptra_top_dut (
     .BootFSM_BrkPoint(BootFSM_BrkPoint),
 
     .recovery_data_avail(1'b1/*TODO*/),
+    .recovery_image_activated(1'b0/*TODO*/),
 
     //SoC Interrupts
     .cptra_error_fatal    (cptra_error_fatal    ),

src/integration/test_suites/smoke_test_mldsa_rand/smoke_test_mldsa_rand.c

@@ -3144,12 +3144,12 @@ uint32_t mldsa_verifyres [] = {0x89E8DA09,
 0xC6ED2197};
     //Call interrupt init
     init_interrupts();
+    mldsa_io seed;
+    uint32_t sign_rnd[8], entropy[16], privkey[1224], pubkey[648], msg[16], sign[1157], verifyres[16];
 
-    uint32_t seed[8], sign_rnd[8], entropy[16], privkey[1224], pubkey[648], msg[16], sign[1157], verifyres[16];
-
-
+    seed.kv_intf = FALSE;
     for (int i = 0; i < 8; i++)
-        seed[7-i] = ((mldsa_seed[i]<<24) & 0xff000000) |
+        seed.data[7-i] = ((mldsa_seed[i]<<24) & 0xff000000) |
                     ((mldsa_seed[i]<< 8) & 0x00ff0000) |
                     ((mldsa_seed[i]>> 8) & 0x0000ff00) |
                     ((mldsa_seed[i]>>24) & 0x000000ff); //mldsa_seed[i];
@@ -3211,9 +3211,9 @@ uint32_t mldsa_verifyres [] = {0x89E8DA09,
     mldsa_zeroize();
     cptra_intr_rcv.mldsa_notif = 0;
 
-    mldsa_verifying_flow(msg, pubkey, sign, verifyres);
-    mldsa_zeroize();
-    cptra_intr_rcv.mldsa_notif = 0;
+    // mldsa_verifying_flow(msg, pubkey, sign, verifyres);
+    // mldsa_zeroize();
+    // cptra_intr_rcv.mldsa_notif = 0;
 
     printf("%c",0xff); //End the test
 

src/integration/test_suites/smoke_test_mldsa_rand/smoke_test_mldsa_rand.yml

@@ -1,3 +1,3 @@
 ---
 seed: 1
-testname: smoke_test_mldsa
+testname: smoke_test_mldsa_rand

src/riscv_core/veer_el2/rtl/common_defines.sv

@@ -16,9 +16,9 @@
 
 
 // NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
-// This is an automatically generated file by cwhitehead on Wed Nov 13 10:25:09 PST 2024
+// This is an automatically generated file by cwhitehead on Wed Nov 20 18:12:03 PST 2024
 //
-// cmd:    veer -target=default_ahb -set=ret_stack_size=8 -set=btb_enable=1 -set=btb_fullya=0 -set=btb_size=512 -set=bht_size=512 -set=div_bit=4 -set=div_new=1 -set=dccm_enable=1 -set=dccm_num_banks=4 -set=dccm_region=0x5 -set=dccm_offset=0x00000 -set=dccm_size=128 -set=dma_buf_depth=5 -set=fast_interrupt_redirect=1 -set=icache_enable=0 -set=icache_waypack=1 -set=icache_ecc=1 -set=icache_size=16 -set=icache_2banks=1 -set=icache_num_ways=2 -set=icache_bypass_enable=1 -set=icache_num_bypass=2 -set=icache_num_tag_bypass=2 -set=icache_tag_bypass_enable=1 -set=iccm_enable=1 -set=iccm_num_banks=4 -set=iccm_region=0x4 -set=iccm_offset=0x0 -set=iccm_size=128 -set=lsu_stbuf_depth=4 -set=lsu_num_nbload=4 -set=load_to_use_plus1=0 -set=pic_2cycle=0 -set=pic_region=0x6 -set=pic_offset=0 -set=pic_size=32 -set=pic_total_int=31 -set=dma_buf_depth=5 -set=timer_legal_en=1 -set=bitmanip_zba=1 -set=bitmanip_zbb=1 -set=bitmanip_zbc=1 -set=bitmanip_zbe=0 -set=bitmanip_zbf=0 -set=bitmanip_zbp=0 -set=bitmanip_zbr=0 -set=bitmanip_zbs=1 -set=pmp_entries=64 -set=reset_vec=0x00000000 -fpga_optimize=0 -snapshot=20241106_cptra_en_pmp 
+// cmd:    veer -target=default_ahb -set=ret_stack_size=8 -set=btb_enable=1 -set=btb_fullya=0 -set=btb_size=512 -set=bht_size=512 -set=div_bit=4 -set=div_new=1 -set=dccm_enable=1 -set=dccm_num_banks=4 -set=dccm_region=0x5 -set=dccm_offset=0x00000 -set=dccm_size=128 -set=dma_buf_depth=5 -set=fast_interrupt_redirect=1 -set=icache_enable=0 -set=icache_waypack=1 -set=icache_ecc=1 -set=icache_size=16 -set=icache_2banks=1 -set=icache_num_ways=2 -set=icache_bypass_enable=1 -set=icache_num_bypass=2 -set=icache_num_tag_bypass=2 -set=icache_tag_bypass_enable=1 -set=iccm_enable=1 -set=iccm_num_banks=4 -set=iccm_region=0x4 -set=iccm_offset=0x0 -set=iccm_size=128 -set=lsu_stbuf_depth=4 -set=lsu_num_nbload=4 -set=load_to_use_plus1=0 -set=pic_2cycle=0 -set=pic_region=0x6 -set=pic_offset=0 -set=pic_size=32 -set=pic_total_int=31 -set=dma_buf_depth=5 -set=timer_legal_en=1 -set=bitmanip_zba=1 -set=bitmanip_zbb=1 -set=bitmanip_zbc=1 -set=bitmanip_zbe=0 -set=bitmanip_zbf=0 -set=bitmanip_zbp=0 -set=bitmanip_zbr=0 -set=bitmanip_zbs=1 -set=pmp_entries=64 -set=reset_vec=0x00000000 -fpga_optimize=0 -snapshot=20241120_latest_fixes 
 //
 `ifndef RV_COMMON_DEFINES
 `define RV_COMMON_DEFINES

src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv

@@ -133,7 +133,10 @@ import el2_pkg::*;
    input logic                         rst_l,        // This includes both top rst and debug rst
    input logic                         dbg_rst_l,
    input logic                         clk_override,
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input logic                         scan_mode
+   /*verilator coverage_on*/
 );
 
 

src/riscv_core/veer_el2/rtl/dec/el2_dec.sv

@@ -320,7 +320,10 @@ module el2_dec
     output logic dec_tlu_icm_clk_override,    // override ICCM clock domain gating
 
     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
+    // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+    /*verilator coverage_off*/
     input  logic scan_mode               // Flop scan mode control
+    /*verilator coverage_on*/
 
 );
 

src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv

@@ -196,7 +196,10 @@ import el2_pkg::*;
 
    output logic       dec_div_active,                 // non-block divide is active
 
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic       scan_mode
+   /*verilator coverage_on*/
    );