Skip to content

Commit

Permalink
[RTL] Convert AXI_ID to AXI_USER (#642)
Browse files Browse the repository at this point in the history 
* Convert AXI_ID to AXI_USER

* MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-axi-user' with updated timestamp and hash after successful run

* Revert default user value of 1 - this is driven in TB when needed

* MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-axi-user' with updated timestamp and hash after successful run
  • Loading branch information
@calebofearth
calebofearth authored Nov 19, 2024
1 parent 227b1d5 commit 4ae54c3
Show file tree
Hide file tree
Showing 22 changed files with 729 additions and 729 deletions.
2 changes: 1 addition & 1 deletion .github/workflow_metadata/pr_hash
View file
Original file line number Diff line number Diff line change
@@ -1 +1 @@
fa1eb0583cba1d002083811627ac6aa3cc5abec5b97928888a2b12b4cd8b15e8437d996c3bc459941be6c28c4b5ab5c3
6104519ceefcd79a47c8c890b053f79f50e15d8213ab0685984df75f95b1273d5eff69ea0dc07cd2d53536d9ed52f88a
2 changes: 1 addition & 1 deletion .github/workflow_metadata/pr_timestamp
View file
Original file line number Diff line number Diff line change
@@ -1 +1 @@
1731724731
1732036724
88 changes: 44 additions & 44 deletions src/integration/rtl/caliptra_reg.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5043,8 +5043,8 @@
#define MBOX_CSR_MBOX_LOCK (0x0)
#define MBOX_CSR_MBOX_LOCK_LOCK_LOW (0)
#define MBOX_CSR_MBOX_LOCK_LOCK_MASK (0x1)
#define CLP_MBOX_CSR_MBOX_ID (0x30020004)
#define MBOX_CSR_MBOX_ID (0x4)
#define CLP_MBOX_CSR_MBOX_USER (0x30020004)
#define MBOX_CSR_MBOX_USER (0x4)
#define CLP_MBOX_CSR_MBOX_CMD (0x30020008)
#define MBOX_CSR_MBOX_CMD (0x8)
#define CLP_MBOX_CSR_MBOX_DLEN (0x3002000c)
Expand Down Expand Up @@ -5544,42 +5544,42 @@
#define SOC_IFC_REG_CPTRA_SECURITY_STATE_SCAN_MODE_MASK (0x8)
#define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_LOW (4)
#define SOC_IFC_REG_CPTRA_SECURITY_STATE_RSVD_MASK (0xfffffff0)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (0x30030048)
#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_0 (0x48)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (0x3003004c)
#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_1 (0x4c)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (0x30030050)
#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_2 (0x50)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (0x30030054)
#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_3 (0x54)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (0x30030058)
#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_ID_4 (0x58)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (0x3003005c)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0 (0x5c)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_0_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (0x30030060)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1 (0x60)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_1_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (0x30030064)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2 (0x64)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_2_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (0x30030068)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3 (0x68)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_3_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (0x3003006c)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4 (0x6c)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_ID_LOCK_4_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (0x30030070)
#define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_ID (0x70)
#define CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (0x30030074)
#define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK (0x74)
#define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_TRNG_AXI_ID_LOCK_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 (0x30030048)
#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_0 (0x48)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 (0x3003004c)
#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_1 (0x4c)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 (0x30030050)
#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_2 (0x50)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 (0x30030054)
#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_3 (0x54)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 (0x30030058)
#define SOC_IFC_REG_CPTRA_MBOX_VALID_AXI_USER_4 (0x58)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (0x3003005c)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0 (0x5c)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_0_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (0x30030060)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1 (0x60)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_1_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (0x30030064)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2 (0x64)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_2_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (0x30030068)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3 (0x68)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_3_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (0x3003006c)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4 (0x6c)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_MBOX_AXI_USER_LOCK_4_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER (0x30030070)
#define SOC_IFC_REG_CPTRA_TRNG_VALID_AXI_USER (0x70)
#define CLP_SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK (0x30030074)
#define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK (0x74)
#define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_TRNG_AXI_USER_LOCK_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_0 (0x30030078)
#define SOC_IFC_REG_CPTRA_TRNG_DATA_0 (0x78)
#define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_1 (0x3003007c)
Expand Down Expand Up @@ -5690,12 +5690,12 @@
#define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK (0x1)
#define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW (1)
#define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK (0x2)
#define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (0x30030108)
#define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_ID (0x108)
#define CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (0x3003010c)
#define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK (0x10c)
#define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_FUSE_AXI_ID_LOCK_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER (0x30030108)
#define SOC_IFC_REG_CPTRA_FUSE_VALID_AXI_USER (0x108)
#define CLP_SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK (0x3003010c)
#define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK (0x10c)
#define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_LOW (0)
#define SOC_IFC_REG_CPTRA_FUSE_AXI_USER_LOCK_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0 (0x30030110)
#define SOC_IFC_REG_CPTRA_WDT_CFG_0 (0x110)
#define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1 (0x30030114)
Expand Down
Loading

0 comments on commit 4ae54c3

Please sign in to comment.