Merge pull request #168 from chipsalliance/dev-msft-20230726

Merge dev-msft-20230726  --> dev-msft

README.md

@@ -14,7 +14,7 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Caliptra Hands-On Guide** #
-_*Last Update: 2023/06/08*_
+_*Last Update: 2023/07/28*_
 
 
 ## **Tools Used** ##
@@ -59,11 +59,11 @@ with the provided Makefile for compiling test C programs.
 1. Install from this repository:
     - https://github.com/riscv-collab/riscv-gnu-toolchain
     - Follow the included README in that repository for installation instructions
-1. The most recently tested toolchain build that was confirmed to work was 2023-04-29
+2. The most recently tested toolchain build that was confirmed to work was 2023-04-29
     - https://github.com/riscv-collab/riscv-gnu-toolchain/releases/tag/2023.04.29
-1. A compatible tool installation requires newlib cross-compiler, multilib support, and the zicsr/zifencei extensions. Use this configure command:
+3. A compatible tool installation requires newlib cross-compiler, multilib support, and the zicsr/zifencei extensions. Use this configure command:
     - `./configure --enable-multilib --prefix=/path/to/tools/riscv-gnu/2023.04.29 --with-multilib-generator="rv32imc-ilp32--a*zicsr*zifencei"`
-1. Use `make` instead of `make linux` to install the tool (using newlib option)
+4. Use `make` instead of `make linux` to install the tool (using newlib option)
 
 ## **ENVIRONMENT VARIABLES** ##
 Required for simulation:<BR>
@@ -138,35 +138,35 @@ The "Integration" sub-component contains the top-level fileset for Caliptra. `sr
 
 ### VCS Steps: ###
 1. Setup tools, add to PATH (ensure riscv64-unknown-elf-gcc is also available)
-1. Define all environment variables above
+2. Define all environment variables above
     - For the initial test run after downloading repository, `iccm_lock` is recommended for TESTNAME
-1. Create a run folder for build outputs (and cd to it)
-1. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for `iccm_lock` test). To do this, copy `iccm_lock.hex` to the run directory and rename to `program.hex`. `dccm.hex` should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
-1. Invoke `${CALIPTRA_ROOT}/tools/scripts/Makefile` with target 'program.hex' to produce SRAM initialization files from the firmware found in `src/integration/test_suites/${TESTNAME}`
+3. Create a run folder for build outputs (and cd to it)
+4. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for `iccm_lock` test). To do this, copy `iccm_lock.hex` to the run directory and rename to `program.hex`. `dccm.hex` should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
+5. Invoke `${CALIPTRA_ROOT}/tools/scripts/Makefile` with target 'program.hex' to produce SRAM initialization files from the firmware found in `src/integration/test_suites/${TESTNAME}`
     - E.g.: `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile program.hex`
-1. Compile complete project using `src/integration/config/caliptra_top_tb.vf` as a compilation target in VCS. When running the `vcs` command to generate simv, users should ensure that `caliptra_top_tb` is explicitly specified as the top-level component in their command to ensure this is the sole "top" that gets simulated.
-1. Simulate project with `caliptra_top_tb` as the top target
+6. Compile complete project using `src/integration/config/caliptra_top_tb.vf` as a compilation target in VCS. When running the `vcs` command to generate simv, users should ensure that `caliptra_top_tb` is explicitly specified as the top-level component in their command to ensure this is the sole "top" that gets simulated.
+7. Simulate project with `caliptra_top_tb` as the top target
 
 ### Verilator Steps: ###
 1. Setup tools, add to PATH (ensure Verilator, GCC, and riscv64-unknown-elf-gcc are available)
-1. Define all environment variables above
+2. Define all environment variables above
     - For the initial test run after downloading repository, `iccm_lock` is recommended for TESTNAME
-1. Create a run folder for build outputs
+3. Create a run folder for build outputs
     - Recommended to place run folder under `${CALIPTRA_WORKSPACE}/scratch/$USER/verilator/<date>`
-1. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for `iccm_lock` test). To do this, copy `iccm_lock.hex` to the run directory and rename to `program.hex`. `dccm.hex` should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
-1. Run Caliptra/tools/scripts/Makefile, which provides steps to run a top-level simulation in Verilator
+4. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for `iccm_lock` test). To do this, copy `iccm_lock.hex` to the run directory and rename to `program.hex`. `dccm.hex` should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
+5. Run Caliptra/tools/scripts/Makefile, which provides steps to run a top-level simulation in Verilator
     - Example command:
         `make -C <path/to/run/folder> -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=${TESTNAME} debug=1 verilator`
     - NOTE: `debug=1` is optional; if provided, the verilator run will produce a .vcd file with waveform information
     - NOTE: `TESTNAME=${TESTNAME}` is optional; if not provided, test defaults to value of TESTNAME environment variable, then to `iccm_lock`
     - NOTE: Users may wish to produce a run log by piping the make command to a tee command, e.g.:
         `make ... <args> ... | tee <path/to/run/folder>/verilate.log`
-1. Users have the option to run the entire suite of smoke tests using the provided python script `run_verilator_l0_regression.py`
+6. Users have the option to run the entire suite of smoke tests using the provided python script `run_verilator_l0_regression.py`
     1. Ensure Python 3.9.2 is available by adding to the $PATH variable
-    1. Run the script with:
+    2. Run the script with:
         `python3 run_verilator_l0_regression.py`
-    1. NOTE: The script automatically creates run output folders at `${CALIPTRA_WORKSPACE}/scratch/$USER/verilator/<timestamp>/<testname>` for each test run
-    1. NOTE: The output folder is populated with a run log that reports the run results and pass/fail status
+    3. NOTE: The script automatically creates run output folders at `${CALIPTRA_WORKSPACE}/scratch/$USER/verilator/<timestamp>/<testname>` for each test run
+    4. NOTE: The output folder is populated with a run log that reports the run results and pass/fail status
 
 ### UVM Testbench Steps for `caliptra_top`: <BR>
 
@@ -179,16 +179,18 @@ The UVM Framework generation tool was used to create the baseline UVM testbench
 
 Steps:<BR>
 1. Compile UVM 1.1d library
-1. Compile the AHB/APB QVIP source
-1. Compile the UVMF wrapper for APB/AHB in Caliptra/src/libs/uvmf
-1. Compile the `verification_ip` provided for `soc_ifc` found in `Caliptra/src/soc_ifc/uvmf_soc_ifc`
-1. Compile the `caliptra_top` testbench found in `Caliptra/src/integration/uvmf_caliptra_top`
-1. `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv` is the top-level TB wrapper for the system
-1. Select a test to run from the set of tests in `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src`
-1. Provide `+UVM_TESTNAME=<test>` argument to simulation
+2. Compile the AHB/APB QVIP source
+3. Compile the UVMF wrapper for APB/AHB in Caliptra/src/libs/uvmf
+4. Compile the `verification_ip` provided for `soc_ifc` found in `Caliptra/src/soc_ifc/uvmf_soc_ifc`
+5. Compile the `caliptra_top` testbench found in `Caliptra/src/integration/uvmf_caliptra_top`
+6. `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv` is the top-level TB wrapper for the system
+7. Select a test to run from the set of tests in `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src`
+8. Provide `+UVM_TESTNAME=<test>` argument to simulation
 
+## **Regression Tests** ##
+
+Only tests from teh L0 Regression List should be run. 
 ## **NOTES** ##
 
-* The internal registers are auto rendered at the [GitHub
-  page](https://chipsalliance.github.io/caliptra-rtl/main/internal-regs)
+* The internal registers are auto rendered at the [GitHub page](https://chipsalliance.github.io/caliptra-rtl/main/internal-regs)
 * So are the [external registers](https://chipsalliance.github.io/caliptra-rtl/main/external-regs)

Release_Notes.md

@@ -14,7 +14,7 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Release Notes** #
-_*Last Update: 2023/07/10*_
+_*Last Update: 2023/07/26*_
 
 ## Rev 0p8 ##
 

etc/pipelines/github-nightly-directed-pipeline.yml

@@ -138,6 +138,21 @@ stages:
               - path: '${WORKSPACE}/Caliptra/src/sha256/stimulus/testsuites/sha256_nightly_directed_regression.yml'
               - timeout: 60 
 
+        - doe_core_cbc_tb:
+          - display_name: 'DOE_CORE_CBC_TB'
+          - enabled: true
+          - configspec_name: 'integration_lib'
+          - dut: 'doe_core_cbc_tb'
+          - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/doe/coverage/config/doe_cm_hier.cfg --submit-resource-args RAM/28000'
+          - testsuites:
+            - nightly_directed:
+              - enabled: true
+              - configspec_name: 'integration_lib'
+              - dut: 'doe_core_cbc_tb'
+              - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
+              - path: '${WORKSPACE}/Caliptra/src/doe/stimulus/testsuites/doe_nightly_directed_regression.yml'
+              - timeout: 60 
+
         - soc_ifc_tb:
             - display_name: 'SOC_IFC_TB'
             - enabled: true

src/datavault/rtl/dv.sv

@@ -104,17 +104,17 @@ always_comb begin: datavault
     end
 
     //Non-Sticky Data Vault Regs & Controls
-    for (int entry = 0; entry < NONSTICKY_DV_NUM_ENTRIES; entry++) begin
-       dv_reg_hwif_in.NonStickyDataVaultCtrl[entry].lock_entry.swwel = dv_reg_hwif_out.NonStickyDataVaultCtrl[entry].lock_entry.value;
+    for (int entry = 0; entry < DV_NUM_ENTRIES; entry++) begin
+       dv_reg_hwif_in.DataVaultCtrl[entry].lock_entry.swwel = dv_reg_hwif_out.DataVaultCtrl[entry].lock_entry.value;
        for (int dword = 0; dword < DV_NUM_DWORDS; dword++) begin
-           dv_reg_hwif_in.NONSTICKY_DATA_VAULT_ENTRY[entry][dword].data.swwel = dv_reg_hwif_out.NonStickyDataVaultCtrl[entry].lock_entry.value;
+           dv_reg_hwif_in.DATA_VAULT_ENTRY[entry][dword].data.swwel = dv_reg_hwif_out.DataVaultCtrl[entry].lock_entry.value;
        end
     end
 
     //Non-Sticky Generic Lockable Registers in the Data Vault
-    for (int entry = 0; entry < NONSTICKY_LOCK_SCRATCH_NUM_ENTRIES; entry++) begin
-       dv_reg_hwif_in.NonStickyLockableScratchRegCtrl[entry].lock_entry.swwel = dv_reg_hwif_out.NonStickyLockableScratchRegCtrl[entry].lock_entry.value;
-       dv_reg_hwif_in.NonStickyLockableScratchReg[entry].data.swwel  = dv_reg_hwif_out.NonStickyLockableScratchRegCtrl[entry].lock_entry.value;
+    for (int entry = 0; entry < LOCK_SCRATCH_NUM_ENTRIES; entry++) begin
+       dv_reg_hwif_in.LockableScratchRegCtrl[entry].lock_entry.swwel = dv_reg_hwif_out.LockableScratchRegCtrl[entry].lock_entry.value;
+       dv_reg_hwif_in.LockableScratchReg[entry].data.swwel  = dv_reg_hwif_out.LockableScratchRegCtrl[entry].lock_entry.value;
     end
 
     //Sticky Generic Lockable Registers in the Data Vault

src/datavault/rtl/dv_defines_pkg.sv

@@ -21,8 +21,8 @@ package dv_defines_pkg;
     parameter DV_DATA_W = 32;
 
     parameter STICKY_DV_NUM_ENTRIES = 10;
-    parameter NONSTICKY_DV_NUM_ENTRIES = 10;
-    parameter NONSTICKY_LOCK_SCRATCH_NUM_ENTRIES = 10;
+    parameter DV_NUM_ENTRIES = 10;
+    parameter LOCK_SCRATCH_NUM_ENTRIES = 10;
     parameter STICKY_LOCK_SCRATCH_NUM_ENTRIES = 8;
     parameter NONSTICKY_SCRATCH_NUM_ENTRIES = 8;
     parameter DV_NUM_DWORDS = 12;

src/datavault/rtl/dv_reg.rdl

@@ -19,51 +19,53 @@ addrmap dv_reg {
     signal {activelow; async;} hard_reset_b;
 
     // Sticky DataVault registers
-    field StickyDataVaultEntry    {desc="DataVault Entry"; sw=rw; hw=na; swwel=true; resetsignal = hard_reset_b;};
+    field StickyDataVaultEntry    {desc="DataVault Entry (cleared on hard reset)"; sw=rw; hw=na; swwel=true; resetsignal = hard_reset_b;};
     reg StickyDataVaultReg    {StickyDataVaultEntry data[32]=0;}; //generic reg for DataVault
 
-    // NonSticky DataVault registers (reset on warm reset)
-    field NonStickyDataVaultEntry {desc="DataVault Entry"; sw=rw; hw=na; swwel=true; resetsignal = reset_b;};
-    reg NonStickyDataVaultReg {NonStickyDataVaultEntry data[32]=0;}; //generic reg for DataVault
+    // Sticky DataVault registers (reset on hard reset)
+    field DataVaultEntry {desc="DataVault Entry (cleared on hard reset)"; sw=rw; hw=na; swwel=true; resetsignal = hard_reset_b;};
+    reg DataVaultReg {DataVaultEntry data[32]=0;}; //generic reg for DataVault
 
     // ============== Data Vault Registers ===========================
     reg {
-        desc="Controls for the Sticky Data Vault Entries";
+        desc="Controls for the Sticky Data Vault Entries (cleared on hard reset)";
         field {desc="Lock writes to this entry. Writes will be suppressed when locked.";
-               sw=rw; swwel=true; hw=r; resetsignal=hard_reset_b;} lock_entry=0; //Shoud reflect NONSTICKY_DV_NUM_ENTRIES from kv_defines_pkg.sv
+               sw=rw; swwel=true; hw=r; resetsignal=hard_reset_b;} lock_entry=0; //Shoud reflect STICKY_DV_NUM_ENTRIES from dv_defines_pkg.sv
     } StickyDataVaultCtrl[10];
 
-    StickyDataVaultReg     STICKY_DATA_VAULT_ENTRY[10][12];//Shoud reflect STICKY_DV_NUM_ENTRIES and DV_NUM_DWORDS from kv_defines_pkg.sv
+    StickyDataVaultReg     STICKY_DATA_VAULT_ENTRY[10][12];//Shoud reflect STICKY_DV_NUM_ENTRIES and DV_NUM_DWORDS from dv_defines_pkg.sv
 
     reg {
-        desc="Controls for the Non-Sticky Data Vault Entries";
+        desc="Controls for the Data Vault Entries (cleared on warm reset)";
         field {desc="Lock writes to this entry. Writes will be suppressed when locked.";
-               sw=rw; swwel=true; hw=r; resetsignal=core_only_rst_b;} lock_entry=0; //Shoud reflect STICKY_DV_NUM_ENTRIES and DV_NUM_DWORDS from kv_defines_pkg.sv
-    } NonStickyDataVaultCtrl[10];// CAREFUL with the address extensions
+               sw=rw; swwel=true; hw=r; resetsignal=core_only_rst_b;} lock_entry=0; //Shoud reflect DV_NUM_ENTRIES and DV_NUM_DWORDS from dv_defines_pkg.sv
+    } DataVaultCtrl[10];// CAREFUL with the address extensions
 
-    NonStickyDataVaultReg  NONSTICKY_DATA_VAULT_ENTRY[10][12];//Shoud reflect NONSTICKY_DV_NUM_ENTRIES and DV_NUM_DWORDS from kv_defines_pkg.sv
+    DataVaultReg  DATA_VAULT_ENTRY[10][12];//Shoud reflect DV_NUM_ENTRIES and DV_NUM_DWORDS from dv_defines_pkg.sv
 
     reg {
-        desc="Non-Sticky Scratch Register Controls";
+        desc="Scratch Register Controls (cleared on warm reset)";
         field {desc="Lock writes to the Scratch registers. Writes will be suppressed when locked.";
                sw=rw; swwel=true; hw=r; resetsignal=core_only_rst_b;} lock_entry=0;
-    } NonStickyLockableScratchRegCtrl[10]; //Shoud reflect NONSTICKY_SCRATCH_NUM_ENTRIES from kv_defines_pkg.sv & CAREFUL with the address extensions
+    } LockableScratchRegCtrl[10]; //Shoud reflect LOCK_SCRATCH_NUM_ENTRIES from dv_defines_pkg.sv & CAREFUL with the address extensions
 
     reg {
-       field {sw=rw; swwel=true; hw=na; resetsignal=reset_b;} data[32]=0;
-    } NonStickyLockableScratchReg[10]; //Shoud reflect NONSTICKY_LOCKQ_SCRATCH_NUM_ENTRIES from kv_defines_pkg.sv
+       desc="Scratch Register Entrie (cleared on hard reset)";
+       field {sw=rw; swwel=true; hw=na; resetsignal=hard_reset_b;} data[32]=0;
+    } LockableScratchReg[10]; //Shoud reflect LOCK_SCRATCH_NUM_ENTRIES from dv_defines_pkg.sv
 
     reg {
        field {sw=rw; hw=na; resetsignal=reset_b;} data[32]=0;
-    } NonStickyGenericScratchReg[8]; //Shoud reflect NONSTICKY_SCRATCH_NUM_ENTRIES from kv_defines_pkg.sv & CAREFUL with the address extensions
+    } NonStickyGenericScratchReg[8]; //Shoud reflect NONSTICKY_SCRATCH_NUM_ENTRIES from dv_defines_pkg.sv & CAREFUL with the address extensions
 
     reg {
-        desc="Sticky Scratch Register Controls";
+        desc="Sticky Scratch Register Controls (cleared on hard reset)";
         field {desc="Lock writes to the Scratch registers. Writes will be suppressed when locked.";
                sw=rw; swwel=true; hw=r; resetsignal=hard_reset_b;} lock_entry=0;
     } StickyLockableScratchRegCtrl[8]; //should reflect STICKY_LOCKQ_SCRATCH_NUM_ENTRIES
 
     reg {
+       desc="Sticky Scratch Register Entries (cleared on hard reset)";
        field {sw=rw; swwel=true; hw=na; resetsignal=hard_reset_b;} data[32]=0;
     } StickyLockableScratchReg[8]; //should reflect STICKY_LOCKQ_SCRATCH_NUM_ENTRIES