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[RTL] Remove QSPI/UART and merge AXI module tweaks from FPGA testing #427

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[RTL] Remove QSPI/UART and merge AXI module tweaks from FPGA testing

[RTL] Remove QSPI/UART and merge AXI module tweaks from FPGA testing #427

Triggered via pull request October 31, 2024 19:20
@calebofearthcalebofearth
#619
cwhitehead-msft-demo-cleanup
Status Failure
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Invalid workflow file: .github/workflows/pull_request.yml#L14
error parsing called workflow ".github/workflows/pull_request.yml" -> "./.github/workflows/pre-run-check.yml" : You have an error in your yaml syntax on line 172