SweRVolf 0.7.4

Xilinx XSim support

In addition to official support for ModelSim/QuestaSim and Verilator, SweRVolf can now also be simulated with Vivado XSim (versions 2020.1 and later)

SweRV EL2 support

SweRVolf was originally developed for SweRV EH1 but now also support SweRV EL2 for applicable targets.

Demo application

The Zephyr-based demo application now prints out detected clock frequency of the system as well as the CPU type (EL2/EH1)

Zephyr support

The Zephyr BSP for SweRVolf automatically detects the clock frequency at runtime and calculates timer intervals and UART baudrates accordingly during boot. This allows the same Zephyr binaries to be used on different SweRVolf implementations using different clock speeds.

GPIO remapping

The 32 upper GPIO have been moved on the memory map from 0x80001014 to 0x80001018 to allow space for a GPIO direction word adjacent to each GPIO bank. The upper 32 GPIO have not been used in any know SweRVolf implementation which is why this change is regarded as safe.

Basys3 support

In addition to the Digilent Nexys A7 board, the Digilent Basys3 board is now also supported providing a lower cost alternative for using SweRVolf. The smaller size of the FPGA on the Basys3 board only allows for SweRV EL2, not SweRV EH1

Documentation

An error in the boot switch arrangments was found and corrected for the Nexys A7 target. A link to a port of the Tock OS has also been added together with a link the the project page on LibreCores

SweRVolf 0.7.3

Zephyr 2.4

SweRVolf has now support for Zephyr 2.4. With this, the SweRVolf-specific code and usage instructions for running Zephyr on SweRVolf have been rewritten and should now be much easier to use.

Memory corruption fix

An issue with the DDR controller was discovered that could occasionally ignore writes to RAM. The controller has now been updated and regenerated. All users are encouraged to update because of this critical bug

SweRVolf 0.7.2

SweRV EH1 1.8

The SweRV EH1 CPU has been upgraded to version 1.8. See the SweRV EH1 release notes for more information. Note: SweRV 1.8 requires a version of OpenOCD from Sep 14, 2020, or newer

Software

• Bootloader and testprograms compiles with rv32im by default
• Support for Zephyr 2.2

Other

• Shortened RAM test time to speed up boot
• Added register to read core clock frequency
• Setup mrac to mark top half of memory space as having side-effects
• Increase testbench memory from 64kB to 1MB

SweRVolf 0.7

SweRV EH1 1.6

The SweRV EH1 CPU has been upgraded to version 1.6. See the SweRV EH1 release notes for more information

Reenabled icache

An updated OpenOCD now supports the SweRV instruction cache, which is now reenabled by default. Make sure to use the latest version of OpenOCD

Software interrupts support

New registers have been added to the system controller to allow triggering external interrrupts as well as the NMI. A new timer has been added as well to allow triggering delayed interrupts, e.g. to test wake-up functionality.

Update AXI components

The AXI interconnect and CDC has been updated to newer versions, which are more robust and performant.

Wishbone subsystem

Related to the updated AXI infrastructure, all peripheral controllers and boot ROM has been moved to a separate Wishbone subsystem which is connected to a slave port on the main AXI interconnect. This makes it easier to add more Wishbone-compatible components in the future.

Support for Riviera-PRO

Aldec Riviera-PRO is now a supported simulator, together with QuestaSim, Verilator and VCS. Other simulators supported by Edalize have a good chance of working too (e.g. xcelium) but are not officially supported.

RISCV-compliance compatibility

Updates have been made to the riscv-target files to support the lastest version of the RISC-V compliance test suite

Improved instructions

The project setup instructions have been simplified and changed for correctness

Updated DDR2 controller

The DDR2 controller, generated by LiteDRAM, has been updated and now uses SERV instead of VexRiscV internally to save resources

SweRVolf 0.6

SweRV EH1 1.5

The SweRV EH1 CPU has been upgraded to version 1.5. See the SweRV EH1 release notes for more information

Disabled icache

To work around an issue with gdb, the default SweRVolf configuration is built with out instruction cache. To enable the instruction cache or change other CPU features, change the corresponding options in the core description file and rebuild

Nexys A7 LEDs and switches mapped to GPIO

The GPIO controller has been expanded and the 16 LEDS and switches are mapped to GPIO. See the documentation for more information. The default demo application is also updated to take advantage of the new GPIO

VCS compatibility

A VCS-incompatible issue was found in one of the dependencies of SweRVolf. This has been fixed and the dependency has been updated so that simulations should work with VCS in addition to the officially support of Questasim and Verilator

mtimecmp is readable

A bug that prevented reading back mtimecmp was found and fixed

Unified bootloader

A new unified bootloader replaces the three previous bootloaders. This allows changing the boot mode by setting GPIO in different positions during power-on. See the documentation for more info

Testbench runs at 50MHz

The verilog testbench was wrongly set to simulate a 25MHz clock which was inconsistent with the provided software, which assumes 50MHz for correct UART baud rate and timer tick frequency

SweRVolf 0.5

SPI Flash boot support

The default bootloader will now load an image stored in SPI Flash and execute that. An image suitable for writing to Flash is provided with the release and the documentation contains information on how to program the Flash, load an image in simulation and create your own images.

Zephyr 2.1

The SweRV and SweRVolf BSP has been rewritten for Zephyr 2.1 and now works with an unmodified upstream version of Zephyr. The example applications have been recompiled against Zephyr 2.1

UART bootloader

For FPGA targets, a UART bootloader can be used instead of the SPI Flash boot by selecting the hexloader boot loader. This allows booting by sending an file over UART in the Intel Hex format

SweRVolf 0.4

This release comes with a new UART, SweRV updated to version 1.4 and is now running at 50MHz instead of 25MHz

SweRVolf 0.3

This release adds support for debugging in simulation and on the Nexys A7 target through USB.

It also adds a SweRVolf demo application and builds with SweRV 1.3