add a test for user mode

.github/workflows/test-riscv-dv.yml

@@ -214,6 +214,8 @@ jobs:
               test: riscv_illegal_instr_test
             - iss: whisper
               test: riscv_illegal_instr_test
+            - iss: whisper
+              test: riscv_full_interrupt_test
 
             # FIXME: VeeR specific WARL CSRs behavior in PMP is not implemented
             # in whisper, hence this exclusion list for PMP tests

tools/riscv-dv/Makefile

@@ -70,6 +70,7 @@ RISCV_DV_ARGS = \
     --batch_size $(RISCV_DV_BATCH) \
     --isa rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs \
     --mabi ilp32 \
+    --priv u \
     --custom_target $(PWD) \
     --testlist $(PWD)/testlist.yaml \
     -v -o $(TEST_DIR)

tools/riscv-dv/riscv_core_setting.sv

@@ -4,7 +4,7 @@
 //
 parameter int XLEN = 32;
 parameter satp_mode_t SATP_MODE = BARE;
-privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE};
+privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE, USER_MODE};
 
 // NOTE: To get supported and unsupported instructions compare
 // riscv-dv/src/riscv_instr_pkg.sv and Cores-VeeR-EL2/design/dec/decode files

tools/riscv-dv/testlist.yaml

@@ -125,4 +125,13 @@
     +enable_zbs_extension=1
     +enable_b_extension=1
     +enable_bitmanip_groups=zbf,zbt
+
+- test: riscv_user_mode_rand_test
+  desc: >
+    User mode random instruction test
+  iterations: 100
+  gen_test: riscv_instr_base_test
+  gen_opts: >
+    +instr_cnt=10000
+    +boot_mode=u
   rtl_test: core_base_test