Add proper reset test for DCLS

Signed-off-by: Robert Szczepanski <[email protected]>
chipsalliance · Oct 25, 2024 · fc0b68c · fc0b68c
1 parent aef1531
commit fc0b68c
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Showing 7 changed files with 476 additions and 47 deletions.
diff --git a/verification/block/common.mk b/verification/block/common.mk
@@ -60,5 +60,5 @@ include $(shell cocotb-config --makefiles)/Makefile.sim
 
 # Rules for generating VeeR config
 $(CFGDIR)/common_defines.vh:
-	cd $(CURDIR) && $(CONFIG)/veer.config -fpga_optimize=0
+	cd $(CURDIR) && $(CONFIG)/veer.config -fpga_optimize=0 $(EXTRA_VEER_CONFIG)
 
diff --git a/verification/block/dcls/Makefile b/verification/block/dcls/Makefile
@@ -8,13 +8,17 @@ SRCDIR := $(abspath $(CURDIR)../../../../design)
 TEST_FILES   = $(sort $(wildcard test_*.py))
 
 MODULE      ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
-TOPLEVEL     = el2_veer_lockstep
+TOPLEVEL     = el2_veer_lockstep_wrapper
+
+EXTRA_VEER_CONFIG = -set lockstep_enable=1 -set lockstep_regfile_enable=1
 
 VERILOG_INCLUDE_DIRS += \
 	${RV_ROOT}/testbench \
 	${RV_ROOT}/design/include
 
 VERILOG_SOURCES  = \
+	${SRCDIR}/lib/el2_mem_if.sv \
+	${SRCDIR}/lib/el2_regfile_if.sv \
 	${SRCDIR}/el2_veer_wrapper.sv \
 	${SRCDIR}/el2_mem.sv \
 	${SRCDIR}/el2_pic_ctrl.sv \
@@ -57,6 +61,7 @@ VERILOG_SOURCES  = \
 	${SRCDIR}/dmi/dmi_jtag_to_core_sync.v \
 	${SRCDIR}/dmi/rvjtag_tap.v \
 	${SRCDIR}/lib/el2_lib.sv \
-	$(SRCDIR)/el2_veer_lockstep.sv
+	$(SRCDIR)/el2_veer_lockstep.sv \
+	$(CURDIR)/dcls/el2_veer_lockstep_wrapper.sv
 
 include $(CURDIR)/../common.mk