Add DMI mux with DMI tests #404
Triggered via pull request
January 4, 2024 14:18
robertszczepanski
robertszczepanski
synchronize
#156
Status
Success
Total duration
43s
Artifacts
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verible-format.yml
on: pull_request_target
format-review
36s
Annotations
3 warnings
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format-review:
design/el2_veer_wrapper.sv#L288
[verible-verilog-format] reported by reviewdog 🐶
Raw Output:
design/el2_veer_wrapper.sv:288:- // clk ratio signals
design/el2_veer_wrapper.sv:289:- input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
design/el2_veer_wrapper.sv:290:- input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
design/el2_veer_wrapper.sv:291:- input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
design/el2_veer_wrapper.sv:292:- input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface
design/el2_veer_wrapper.sv:293:-
design/el2_veer_wrapper.sv:294:- // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not)
design/el2_veer_wrapper.sv:295:-
design/el2_veer_wrapper.sv:296:- input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
design/el2_veer_wrapper.sv:297:- input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
design/el2_veer_wrapper.sv:298:-
design/el2_veer_wrapper.sv:299:- input logic timer_int,
design/el2_veer_wrapper.sv:300:- input logic soft_int,
design/el2_veer_wrapper.sv:301:- input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,
design/el2_veer_wrapper.sv:302:-
design/el2_veer_wrapper.sv:303:- output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
design/el2_veer_wrapper.sv:304:- output logic dec_tlu_perfcnt1,
design/el2_veer_wrapper.sv:305:- output logic dec_tlu_perfcnt2,
design/el2_veer_wrapper.sv:306:- output logic dec_tlu_perfcnt3,
design/el2_veer_wrapper.sv:307:-
design/el2_veer_wrapper.sv:308:- // ports added by the soc team
design/el2_veer_wrapper.sv:309:- input logic jtag_tck, // JTAG clk
design/el2_veer_wrapper.sv:310:- input logic jtag_tms, // JTAG TMS
design/el2_veer_wrapper.sv:311:- input logic jtag_tdi, // JTAG tdi
design/el2_veer_wrapper.sv:312:- input logic jtag_trst_n, // JTAG Reset
design/el2_veer_wrapper.sv:313:- output logic jtag_tdo, // JTAG TDO
design/el2_veer_wrapper.sv:314:-
design/el2_veer_wrapper.sv:315:- input logic [31:4] core_id,
design/el2_veer_wrapper.sv:316:-
design/el2_veer_wrapper.sv:317:- // Memory Export Interface
design/el2_veer_wrapper.sv:318:- el2_mem_if.veer_sram_src el2_mem_export,
design/el2_veer_wrapper.sv:319:-
design/el2_veer_wrapper.sv:320:- // external MPC halt/run interface
design/el2_veer_wrapper.sv:321:- input logic mpc_debug_halt_req, // Async halt request
design/el2_veer_wrapper.sv:322:- input logic mpc_debug_run_req, // Async run request
design/el2_veer_wrapper.sv:323:- input logic mpc_reset_run_req, // Run/halt after reset
design/el2_veer_wrapper.sv:324:- output logic mpc_debug_halt_ack, // Halt ack
design/el2_veer_wrapper.sv:325:- output logic mpc_debug_run_ack, // Run ack
design/el2_veer_wrapper.sv:326:- output logic debug_brkpt_status, // debug breakpoint
design/el2_veer_wrapper.sv:327:-
design/el2_veer_wrapper.sv:328:- input logic i_cpu_halt_req, // Async halt req to CPU
design/el2_veer_wrapper.sv:329:- output logic o_cpu_halt_ack, // core response to halt
design/el2_veer_wrapper.sv:330:- output logic o_cpu_halt_status, // 1'b1 indicates core is halted
desig
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format-review:
design/el2_veer_wrapper.sv#L346
[verible-verilog-format] reported by reviewdog 🐶
Raw Output:
design/el2_veer_wrapper.sv:346:- logic active_l2clk;
design/el2_veer_wrapper.sv:347:- logic free_l2clk;
design/el2_veer_wrapper.sv:345:+ logic active_l2clk;
design/el2_veer_wrapper.sv:346:+ logic free_l2clk;
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format-review:
design/el2_veer_wrapper.sv#L503
[verible-verilog-format] reported by reviewdog 🐶
Raw Output:
design/el2_veer_wrapper.sv:503:- wire lsu_axi_awvalid;
design/el2_veer_wrapper.sv:504:- wire lsu_axi_awready;
design/el2_veer_wrapper.sv:505:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid;
design/el2_veer_wrapper.sv:506:- wire [31:0] lsu_axi_awaddr;
design/el2_veer_wrapper.sv:507:- wire [3:0] lsu_axi_awregion;
design/el2_veer_wrapper.sv:508:- wire [7:0] lsu_axi_awlen;
design/el2_veer_wrapper.sv:509:- wire [2:0] lsu_axi_awsize;
design/el2_veer_wrapper.sv:510:- wire [1:0] lsu_axi_awburst;
design/el2_veer_wrapper.sv:511:- wire lsu_axi_awlock;
design/el2_veer_wrapper.sv:512:- wire [3:0] lsu_axi_awcache;
design/el2_veer_wrapper.sv:513:- wire [2:0] lsu_axi_awprot;
design/el2_veer_wrapper.sv:514:- wire [3:0] lsu_axi_awqos;
design/el2_veer_wrapper.sv:515:-
design/el2_veer_wrapper.sv:516:- wire lsu_axi_wvalid;
design/el2_veer_wrapper.sv:517:- wire lsu_axi_wready;
design/el2_veer_wrapper.sv:518:- wire [63:0] lsu_axi_wdata;
design/el2_veer_wrapper.sv:519:- wire [7:0] lsu_axi_wstrb;
design/el2_veer_wrapper.sv:520:- wire lsu_axi_wlast;
design/el2_veer_wrapper.sv:521:-
design/el2_veer_wrapper.sv:522:- wire lsu_axi_bvalid;
design/el2_veer_wrapper.sv:523:- wire lsu_axi_bready;
design/el2_veer_wrapper.sv:524:- wire [1:0] lsu_axi_bresp;
design/el2_veer_wrapper.sv:525:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_bid;
design/el2_veer_wrapper.sv:526:-
design/el2_veer_wrapper.sv:527:- // AXI Read Channels
design/el2_veer_wrapper.sv:528:- wire lsu_axi_arvalid;
design/el2_veer_wrapper.sv:529:- wire lsu_axi_arready;
design/el2_veer_wrapper.sv:530:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_arid;
design/el2_veer_wrapper.sv:531:- wire [31:0] lsu_axi_araddr;
design/el2_veer_wrapper.sv:532:- wire [3:0] lsu_axi_arregion;
design/el2_veer_wrapper.sv:533:- wire [7:0] lsu_axi_arlen;
design/el2_veer_wrapper.sv:534:- wire [2:0] lsu_axi_arsize;
design/el2_veer_wrapper.sv:535:- wire [1:0] lsu_axi_arburst;
design/el2_veer_wrapper.sv:536:- wire lsu_axi_arlock;
design/el2_veer_wrapper.sv:537:- wire [3:0] lsu_axi_arcache;
design/el2_veer_wrapper.sv:538:- wire [2:0] lsu_axi_arprot;
design/el2_veer_wrapper.sv:539:- wire [3:0] lsu_axi_arqos;
design/el2_veer_wrapper.sv:540:-
design/el2_veer_wrapper.sv:541:- wire lsu_axi_rvalid;
design/el2_veer_wrapper.sv:542:- wire lsu_axi_rready;
design/el2_veer_wrapper.sv:543:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_rid;
design/el2_veer_wrapper.sv:544:- wire [63:0] lsu_axi_rdata;
design/el2_veer_wrapper.sv:545:- wire [1:0] lsu_axi_rresp;
design/el2_veer_wrapper.sv:546:- wire lsu_axi_rlast;
design/el2_veer_wrapper.sv:547:-
design/el2_veer_wrapper.sv:548:- //-------------------------- IFU AXI signals--------------------------
design/el2_veer_wrapper.sv:549:- // AXI Write Channels
design/el2_veer_wrapper.sv:550:- wire ifu_axi_awvalid;
design/el2_veer_wrapper.sv:551:- wire ifu_axi_awready;
design/el2_veer_wrapper.sv:552:- wire [pt.IFU_BUS_TAG-1:0] ifu_axi_awid;
design/el2_veer_wrapper.sv:553:- wire [31:0] ifu_axi_awaddr;
design/el2_veer_wrapper.sv:554:- wire [3:0] ifu_axi_awregion;
des
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