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CI #7185

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CI #7185

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Job Run time
bittide-instances synthesis matrix generation
23s
bittide-instances synthesis matrix generation
23s
Build dependencies
2m 22s
Build dependencies
2m 22s
Basic linting
1m 3s
Basic linting
1m 3s
license-check
17s
license-check
17s
bittide-instances hardware-in-the-loop test matrix generation
23s
bittide-instances hardware-in-the-loop test matrix generation
23s
Bittide tests
7m 25s
Bittide tests
7m 25s
bittide-experiments unittests
1m 7s
bittide-experiments unittests
1m 7s
Rust Lints
51s
Rust Lints
51s
Firmware Support Unit Tests
3m 46s
Firmware Support Unit Tests
3m 46s
Firmware Limit Checks
52s
Firmware Limit Checks
52s
bittide-instances doctests
2m 29s
bittide-instances doctests
2m 29s
bittide-instances unittests
3m 14s
bittide-instances unittests
3m 14s
synth (counterReducedPins, pnr)
3m 22s
synth (counterReducedPins, pnr)
3m 22s
synth (elasticBuffer5, pnr)
3m 30s
synth (elasticBuffer5, pnr)
3m 30s
synth (gatherUnit1K, hdl)
2m 28s
synth (gatherUnit1K, hdl)
2m 28s
synth (gatherUnit1KReducedPins, pnr)
3m 53s
synth (gatherUnit1KReducedPins, pnr)
3m 53s
synth (safeDffSynchronizer, pnr)
3m 17s
synth (safeDffSynchronizer, pnr)
3m 17s
synth (scatterUnit1K, hdl)
2m 46s
synth (scatterUnit1K, hdl)
2m 46s
synth (scatterUnit1KReducedPins, pnr)
3m 55s
synth (scatterUnit1KReducedPins, pnr)
3m 55s
synth (si5391Spi, pnr)
5m 17s
synth (si5391Spi, pnr)
5m 17s
synth (stabilityChecker_3_1M, pnr)
3m 19s
synth (stabilityChecker_3_1M, pnr)
3m 19s
synth (switchCalendar1k, hdl)
4m 39s
synth (switchCalendar1k, hdl)
4m 39s
synth (switchCalendar1kReducedPins, pnr)
5m 26s
synth (switchCalendar1kReducedPins, pnr)
5m 26s
synth (boardTestExtended, test)
5m 23s
synth (boardTestExtended, test)
5m 23s
synth (boardTestSimple, test)
5m 3s
synth (boardTestSimple, test)
5m 3s
synth (dnaOverSerial, test)
5m 48s
synth (dnaOverSerial, test)
5m 48s
synth (fincFdecTests, test)
7m 32s
synth (fincFdecTests, test)
7m 32s
synth (swCcTopologyTest, test)
19m 36s
synth (swCcTopologyTest, test)
19m 36s
synth (linkConfigurationTest, test)
14m 9s
synth (linkConfigurationTest, test)
14m 9s
synth (syncInSyncOut, test)
6m 22s
synth (syncInSyncOut, test)
6m 22s
synth (temperatureMonitor, test)
6m 59s
synth (temperatureMonitor, test)
6m 59s
synth (transceiversUpTest, test)
14m 6s
synth (transceiversUpTest, test)
14m 6s
synth (vexRiscvTest, test)
7m 58s
synth (vexRiscvTest, test)
7m 58s
synth (vexRiscvTcpTest, test)
9m 2s
synth (vexRiscvTcpTest, test)
9m 2s
HITL (boardTestExtended, test)
1s
HITL (boardTestExtended, test)
1m 58s
HITL (boardTestSimple, test)
1s
HITL (boardTestSimple, test)
1m 35s
HITL (dnaOverSerial, test)
26s
HITL (dnaOverSerial, test)
1m 35s
HITL (fincFdecTests, test)
1s
HITL (fincFdecTests, test)
1m 17s
HITL (swCcTopologyTest, test)
1s
HITL (swCcTopologyTest, test)
14m 39s
HITL (linkConfigurationTest, test)
1s
HITL (linkConfigurationTest, test)
1m 41s
HITL (syncInSyncOut, test)
1s
HITL (syncInSyncOut, test)
1m 36s
HITL (temperatureMonitor, test)
1s
HITL (temperatureMonitor, test)
1m 43s
HITL (transceiversUpTest, test)
1s
HITL (transceiversUpTest, test)
2m 21s
HITL (vexRiscvTest, test)
1s
HITL (vexRiscvTest, test)
1m 22s
HITL (vexRiscvTcpTest, test)
1s
HITL (vexRiscvTcpTest, test)
1m 51s
Generate clock control report
1s
Generate clock control report
3m 56s
All jobs finished
1s
All jobs finished
4s
6h 12m 20s