Release 1.4.3

Release 1.4.3 (See ERRATA for unsupported features)

• DRAM Data Retention - With DRAM data retention, developers can simply load a new AFI and continue using the data that is persistently kept in the DRAM attached to the FPGA, eliminating unnecessary data movements and greatly improving the overall application performance.
• Virtual Ethernet - Provides a low latency network interface for EC2 F1, that enables high performance hardware acceleration to ethernet based applications on AWS like firewalls, routers and advanced security virtual appliances. With Virtual Ethernet, developers are able to create F1 accelerators that process ethernet packets directly from user-space on the FPGA with high throughput and low-latency.
• Developer AMI v1.5 with Vivado/SDx 2018.2 tools - New FPGA developer AMI supporting Vivado 2018.2 for faster compile times, higher frequencies and improved timing closure

Release 1.4.2

• Fixed SDAccel XOCL driver compile fails that occur on linux kernels greater than 3.10.0-862.3.3.el7.x86_64

Release 1.4.1

Release 1.4.1 (See ERRATA for unsupported features)

• Simulation performance Improvements
  • DDR Behavioural Model - Hardware simulations use an AXI memory model to run 4X faster by skipping DDR initialization. Please refer to this README on how to use this feature in your simulation.
  • DDR Backdoor Loading - Hardware simulation time is reduced by pre-loading data directly into memory models. Please refer to this README for example tests that demonstrate this feature.
• Fixed Issues
  • XOCL Driver update to address synchronization issues.
  • Fixed XOCL driver issues when using ubuntu distribution for Linux OS.
  • Improved Performance for cl_dram_dma Public AFI.
  • SDAccel 3rd party examples updated to use Shell V1.4 DSA.
  • Fixed AFI Manifest generation in IPI flow.
  • HLX button fixed in IPI
  • FPGA Library update

Release 1.4.0

Release 1.4.0 (See ERRATA for unsupported features)

• New Shell Stable: v04261818. Starting with release v1.4.0, the AWS FPGA shell stable has been updated and only supports Xilinx 2017.4 SDx/Vivado. All previous versions of tools and shells are not supported with this developer kit shell release.

  • Shell Release Notes

• The previous shell (v071417d3) will be supported until 09/01/2018. Developers are required to use the developer kit v1.3.X branch for all shell version v071417d3 development.

• Release 1.4.0 greatly improves the performance of the DMA (for interrupt driven DMA on the cl_dram_dma example design). This is accomplished through a combination of shell changes to relax DMA timeouts and a new XDMA software driver option. We have ported the relevant HDK examples to the XDMA driver in this release. EDMA is still supported, and developers can freely choose which DMA driver to use as part of their host application.

Release 1.3.8

Release 1.3.8 (See ERRATA for unsupported features)

• Fixed SDAccel XOCL driver compile fails that occur on linux kernels greater than 3.10.0-693.21.1.el7.x86_64

Release 1.3.7

Release 1.3.7 (See ERRATA for unsupported features)

• Support for Xilinx SDx/Vivado 2017.1 and Xilinx SDx/Vivado 2017.4 . * This release supports Xilinx SDx 2017.4 and 2017.1. The HDK and SDAccel setup scripts configure the development environment based on the tool version found in the PATH environment variable.
  • FPGA developer kit version is listed in hdk_version.txt
  • FPGA developer kit supported tool versions are listed in supported_vivado_versions
  • The compatibility table describes the mapping of developer kit version to FPGA developer AMI version:

Developer Kit Version	Tool Version Supported	Compatible FPGA developer AMI Version
1.3.0-1.3.6	2017.1	v1.3.5
1.3.7-1.3.X	2017.1	v1.3.5-v1.3.X (Xilinx SDx 2017.1)
1.3.7-1.3.X	2017.4	v1.4.0-v1.4.X (Xilinx SDx 2017.4)

• OpenCL dynamic resource optimization – The developer tools automatically remove unused DDR and debug logic to free up resources and reduce compile times. See 2017.4 Migration Document and SDAccel User Guide
• Developers can instantiate up to 60 kernels (up from the max 16 2017.1 supported).
• OpenCL Kernel profiling – During compile time, profiling logic can be automatically inserted to enable generation of kernel profile data. Profile data can be viewed using the SDx IDE under profile summary report and timeline trace report. See chapter 6 within the SDAccel Environment Profiling and Optimization Guide
• OpenCL Hardware Emulation Debug – GDB-like debug allows developers a view into what is going on inside the kernel during hardware emulation. Debug capabilities include start/stop at intermediate points and memory inspection. See chapter 6 within the SDAccel Environment Profiling and Optimization Guide
• Post-synthesis and place/route optimization is now supported in OpenCL development environment. New XOCC options: reuse_synth and reuse_impl
• Customer simulation environment improvements and bug fixes:
  • 8 Additional tests that will help developer with using the simulation environment and shell simulation model
  • Simulation model support for non DW aligned accesses
  • Co-simulation support
• EDMA Driver fixes:
  • Prevent timeouts due to scanning of the BARs for DMA hardware
  • Driver compilation support for 4.14 linux kernel
• HDK improvements and fixes:
  • cl_dram_dma improvements to make enabling/disabling DDRs easier
  • encrypt.tcl now clears out old files
  • URAM example timing improvements
• IPI Improvements:
  • HLS example
  • Script based approach for running the examples

Release 1.3.6d

Errata updates

Release 1.3.6c

Release 1.3.6c (See ERRATA for unsupported features)

• Fixes for SDAccel 1DDR and IPI

Release 1.3.6

Release 1.3.6 (See ERRATA for unsupported features)

• Simulation model bug fix for transfer size of 64 bytes
• Xilinx 2017.1 Patch AR70350 - fixes report_power hangs. Patch is automatically applied during setup scripts using MYVIVADO environment variable
• Updated synthesis scripts with -sv option when calling read_verilog
• Added documentation on us-gov-west-1 (GovCloud US)
• Minor EDMA driver fixes and improvements

Release 1.3.5

Release 1.3.5 (See ERRATA for unsupported features)

• Amazon FPGA Images (AFIs) Tagging - To help with managing AFIs, you can optionally assign your own metadata to each AFI in the form of tags. Tags are managed using the AWS EC2 CLI commands create-tags, describe-tags and delete-tags. Tags are custom key/value pairs that can be used to identify or group EC2 resources, including AFIs. Tags can be used as filters in the describe-fpga-images API to search and filter the AFIs based on the tags you add.
• EDMA driver fixes and improvements, including polled DMA descriptor completion mode which improves performance on smaller IO (<1MB)
• AFI Power metrics and warnings – developers can avoid power violations by monitoring metrics that provide recent FPGA power, maximum FPGA power and average FPGA power. CL designs can use power state pins to help developers throttle CL to avoid power violation.
• Improved IPI 3rd party simulator support
• Simulation model fixes
• SDAccel improvements - Removal of settings64 script from SDAccel setup and switching between DSAs