Release v1.4.17

Updates

• Updated XDMA Driver to allow builds on newer kernels
• Updated documentation on Alveo U200 to F1 platform porting
• Added Vitis 2019.2 Patching for AR#73068

Release v1.4.16

FPGA developer kit now supports Xilinx Vitis/Vivado 2020.1.

We recommend developers upgrade to 2020.1 to benefit from the new features, bug fixes, and optimizations. To upgrade your developer kit, make sure you use the FPGA Developer AMI v1.9.0 and simply update to the latest FPGA developer kit v1.4.16.

New features

• FPGA developer kit now supports Xilinx Vivado/Vitis 2020.1
• Updated Vitis examples to include usage of Vitis Libraries.
• Added documentation and examples to show Xilinx Alveo design migration to F1.
• Re-structured README

Xilinx toolset version support removal

In this release, we have removed support for older Xilinx tool versions: 2017.4, 2018.2, 2018.3. While v1.4.16+ will not support older Xilinx tools, you can still use them using HDK releases v1.4.15a or earlier.

Release v1.4.15a

Bug Fix Release

This fix upgrades DDR IP and regenerates IP outputs to fix the issue described in Xilinx AR#73068

Changes:

• Add upgrade ip changes to the init.tcl file

• Updated the cl_dram_dma public AFI

Release v1.4.15

• AR73068 patching (#608)

  • Added patching mechanism for Vivado AR73068
  • Updated supported versions

• Updated the shell interface spec to reflect current shell (#603)

  • Updated the shell interface spec to reflect current shell and pointed to the DDR Data Retention doc
  • Update hdk/docs/AWS_Shell_Interface_Specification.md

• Enhance DDR Model Build qualifiers in hdk_setup.sh script. (#604)

  • Enhance DDR Model Build qualifiers in hdk_setup.sh script.
  • Enhance the DDR model build's lock file creation+check to not rely on external tools.

• Update Virtual_JTAG_XVC.md (#606)

• Added dma range error to interrupt status register metrics (#591)

  • added dma range error to interrupt status register metrics
  • updated tests to match change to output

• Fixing test_fpga_tools to accomodate dma range error addition. (#609)

  • Fixed the lines where we expect clock group c

Release v1.4.14

Release 1.4.14 (See ERRATA for unsupported features)

• Added a new platform file to fix DDR bandwidth issue
• Add Vitis Debug document

Release v1.4.13

Release 1.4.13 (See ERRATA for unsupported features)

• FPGA developer kit now supports Xilinx Vivado/Vitis 2019.2
• To upgrade, use Developer AMI v1.8.0 on the AWS Marketplace.

Release v1.4.12

• Added supported versions for BJS AMI's
• Added link to the re:Invent 19 F1 workshop
• Fixed missing extern C declaration by PR #473
• Documentation Path fixes from #466, #468 and #470

Release v1.4.11

• FPGA developer kit now supports Xilinx SDx/Vivado 2019.1

  • We recommend developers upgrade to v1.4.11 to benefit from the new features, bug fixes, and optimizations.
  • To upgrade, use Developer AMI v1.7.0 on the AWS Marketplace. The Developer Kit scripts (hdk_setup.sh or sdaccel_setup.sh) will detect the tool version and update the environment based on requirements needed for Xilinx 2019.1 tools.

• New functionality:

  • Added a developer resources section that provides guides on how to setup your own GUI Desktop and compute cluster environment.
  • Developers can now ask for AFI limit increases via the AWS Support Center Console.
    • Create a case to increase your EC2 FPGA service limit from the console.
  • HLx IPI flow updates
    • HLx support for AXI Fast Memory mode.
    • HLx support for 3rd party simulations.
    • HLx support for changes in shell and AWS IP updates(e.g. sh_ddr).

• Bug Fixes:

  • Documentation fixes in the Shell Interface Specification
  • Fixes for forum questions
    • Unable to compile aws_v1_0_vl_rfs.sv in Synopsys VCS
    • Use fpga_mgmt init in HLx runtime
  • New XRT versions added to the XRT Installation Instructions to fix segmentation faults when using xclbin instead of awsxclbin files.

• Deprecations:

  • Removed GUI Setup scripts from AMI v1.7.0 onwards. See the developer resources section that provides guides on how to setup your own GUI Desktop and compute cluster environment.

• Package versions used for validation

  Package	AMI 1.7.0 [2019.1]	AMI 1.6.0 [2018.3]	AMI 1.5.0 [2018.2]	AMI 1.4.0 [2017.4]
  OS	Centos 7.6	Centos 7.6	Centos 7.5, 7.6	Centos 7.4
  kernel	3.10.0-957.27.2.el7.x86_64	3.10.0-957.5.1.el7.x86_64	3.10.0-862.11.6.el7.x86_64, 3.10.0-957.1.3.el7.x86_64	3.10.0-693.21.1.el7.x86_64
  kernel-devel	3.10.0-957.27.2.el7.x86_64	3.10.0-957.5.1.el7.x86_64	3.10.0-862.11.6.el7.x86_64, 3.10.0-957.1.3.el7.x86_64	3.10.0-693.21.1.el7.x86_64
  LIBSTDC++	libstdc++-4.8.5-36.el7_6.2.x86_64	libstdc++-4.8.5-36.el7.x86_64	libstdc++-4.8.5-36.el7.x86_64	libstdc++-4.8.5-16.el7_4.2.x86_64

Release v1.4.10

• New functionality:

  • SDK now sorts the slots in DBDF order. Any scripts or integration maintainers should note that the slot order will be different from previous versions and should make any updates accordingly.

• Bug Fixes:

  • Fixes a bug in the Automatic Traffic Generator (ATG). In SYNC mode, the ATG did not wait for write response transaction before issuing read transactions.
  • Released Xilinx runtime(XRT) version 2018.3.3.2 to fix the following error: symbol lookup error: /opt/xilinx/xrt/lib/libxrt_aws.so: undefined symbol: uuid_parse! discussed in this forum post.
  • This release fixes a bug wherein concurrent AFI load requests on two or more slots resulted in a race condition which sometimes resulted in Error: (20) pci-device-missing
  • This release fixes a issue with coding style of logic which could infer a latch during synthesis in sde_ps_acc module within cl_sde example

Release v1.4.9

• New functionality:

  • Improved AFI load times for pipelined accelerator designs. For more details please see Amazon FPGA image (AFI) pre-fetch and caching features.

• Ease of Use features:

  • Improved SDK Error messaging
  • Improved documentation to help with transition from HLX to HDK command line flows and vice versa
  • Incorporates feedback from aws-fpga Issue 458 by making the init_ddr function, used in design simulations to initialize DDR, more generic by moving out ATG deselection logic to a new deselect_atg_hw task

• Bug Fixes:

  • Fixed Shell simulation model (sh_bfm) issue on PCIM AXI read data channel back pressure which was described in HDK 1.4.8 Errata.
  • Fixed HDK simulation example which demonstrates DMA and PCIM traffic in parallel.