Release v1.3.6 (#386)

Author: kristopk

.gitignore

@@ -95,3 +95,6 @@ vivado*.log
 
 # pytest artifacts
 .cache/
+
+# Patches
+patches/*

FAQs.md

@@ -107,7 +107,7 @@ The developer can create multiple AFIs at no extra cost, up to a defined limited
 
 **Q: What regions are supported?**
 
-AWS FPGA generation and EC2 F1 instances are supported in us-east-1 (N. Virginia), us-west-2 (Oregon) and eu-west-1 (Ireland).
+AWS FPGA generation and EC2 F1 instances are supported in us-east-1 (N. Virginia), us-west-2 (Oregon), eu-west-1 (Ireland) and us-gov-west-1 (GovCloud US).
 
 
 
@@ -205,6 +205,10 @@ Yes. Developers are free to use any IP blocks within the Custom Logic region. Th
 
 
 ## Getting Started
+**Q: What AWS knowledge do I need to learn before I can develop accelerators and run on AWS F1 instances?**
+
+[AWS Getting Started Resource Center](https://aws.amazon.com/getting-started/) has lots of resources to help developers get started.  For F1 development, launching linux virtual machines (EC2) and storing and retrieving files from S3 are required skills.  
+
 **Q: What do I need to get started on building accelerators for FPGA instances?**
 
 Getting started requires downloading the latest HDK and SDK from the AWS FPGA GitHub repository. The HDK and SDK provide the needed code and information for building FPGA code. The HDK provides all the information needed for developing an FPGA image from source code, while the SDK provides all the runtime software for managing the Amazon FPGA Image (AFI) loaded into the F1 instance FPGA.

Jenkinsfile

@@ -81,8 +81,11 @@ if (debug_fdf_uram) {
 // Globals
 //=============================================================================
 
-// Map that contains top level stages
-def top_parallel_stages = [:]
+// Map that contains stages of tests
+
+def initial_tests = [:]
+def secondary_tests = [:]
+def multi_stage_tests = [:]
 
 // Task to Label map
 def task_label = [
@@ -118,7 +121,7 @@ if (is_public_repo())
 
 
 if (test_markdown_links || test_src_headers) {
-    top_parallel_stages['Short Tests'] = {
+    initial_tests['Documentation Tests'] = {
         node(task_label.get('md_links')) {
             checkout scm
             if (test_markdown_links) {
@@ -169,7 +172,7 @@ if (test_markdown_links || test_src_headers) {
 //=============================================================================
 
 if (test_hdk_scripts) {
-    top_parallel_stages['Test HDK Scripts'] = {
+    initial_tests['Test HDK Scripts'] = {
         stage('Test HDK Scripts') {
             String report_file = 'test_hdk_scripts.xml'
             node(task_label.get('source_scripts')) {
@@ -194,7 +197,7 @@ if (test_hdk_scripts) {
 }
 
 if (test_fpga_tools) {
-    top_parallel_stages['Test FPGA Tools 1 Slot'] = {
+    initial_tests['Test FPGA Tools 1 Slot'] = {
         stage('Test FPGA Tools 1 Slot') {
             String report_file = 'test_fpga_tools.xml'
             node(task_label.get('runtime')) {
@@ -216,7 +219,7 @@ if (test_fpga_tools) {
             }
         }
     }
-    top_parallel_stages['Test FPGA Tools All Slots'] = {
+    initial_tests['Test FPGA Tools All Slots'] = {
         stage('Test FPGA Tools All Slots') {
             String report_file = 'test_fpga_tools_all_slots.xml'
             node(task_label.get('runtime-all-slots')) {
@@ -241,7 +244,7 @@ if (test_fpga_tools) {
 }
 
 if (test_sims) {
-    top_parallel_stages['Run Sims'] = {
+    multi_stage_tests['Run Sims'] = {
         stage('Run Sims') {
             def cl_names = ['cl_dram_dma', 'cl_hello_world']
             def sim_nodes = [:]
@@ -280,7 +283,7 @@ if (test_sims) {
 }
 
 if (test_edma) {
-    top_parallel_stages['Test EDMA Driver'] = {
+    secondary_tests['Test EDMA Driver'] = {
         stage('Test EDMA Driver') {
             node(task_label.get('runtime')) {
                 echo "Test EDMA Driver"
@@ -301,7 +304,7 @@ if (test_edma) {
                 } finally {
                     if (fileExists(report_file)) {
                         junit healthScaleFactor: 10.0, testResults: report_file
-                        archiveArtifacts artifacts: "sdk/tests/fio_dma_tools/scripts/*.csv", fingerprint: true
+                        // archiveArtifacts artifacts: "sdk/tests/fio_dma_tools/scripts/*.csv", fingerprint: true
                     }
                     else {
                         echo "Pytest wasn't run for stage. Report file not generated: ${report_file}"
@@ -313,7 +316,7 @@ if (test_edma) {
 }
 
 if (test_xdma) {
-    top_parallel_stages['Test XDMA Driver'] = {
+    secondary_tests['Test XDMA Driver'] = {
         stage('Test XDMA Driver') {
             node(task_label.get('runtime')) {
                 echo "Test XDMA Driver"
@@ -333,15 +336,15 @@ if (test_xdma) {
                     throw exc
                 } finally {
                     junit healthScaleFactor: 10.0, testResults: report_file
-                    archiveArtifacts artifacts: "sdk/tests/fio_dma_tools/scripts/*.csv", fingerprint: true
+                    //archiveArtifacts artifacts: "sdk/tests/fio_dma_tools/scripts/*.csv", fingerprint: true
                 }
             }
         }
     }
 }
 
 if (test_runtime_software) {
-    top_parallel_stages['Test Runtime Software'] = {
+    multi_stage_tests['Test Runtime Software'] = {
         stage('Test Runtime Software') {
             def nodes = [:]
             def node_types = ['runtime', 'runtime-all-slots']
@@ -389,7 +392,7 @@ if (test_runtime_software) {
 }
 
 if (test_dcp_recipes) {
-    top_parallel_stages['Test DCP Recipes'] = {
+    multi_stage_tests['Test DCP Recipes'] = {
         stage('Test DCP Recipes') {
             def nodes = [:]
             for (cl in dcp_recipe_cl_names) {
@@ -433,7 +436,7 @@ if (test_dcp_recipes) {
 if (test_hdk_fdf) {
     // Top level stage for FDF
     // Each CL will have its own parallel FDF stage under this one.
-    top_parallel_stages['HDK_FDF'] = {
+    multi_stage_tests['HDK_FDF'] = {
         stage('HDK FDF') {
             def fdf_stages = [:]
             for (x in fdf_test_names) {
@@ -602,7 +605,7 @@ if (test_hdk_fdf) {
 //=============================================================================
 
 if (test_sdaccel_scripts) {
-    top_parallel_stages['Test SDAccel Scripts'] = {
+    initial_tests['Test SDAccel Scripts'] = {
         stage('Test SDAccel Scripts') {
             String report_file = 'test_sdaccel_scripts.xml'
             node(task_label.get('source_scripts')) {
@@ -627,7 +630,7 @@ if (test_sdaccel_scripts) {
 }
 
 if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
-    top_parallel_stages['Run SDAccel Tests'] = {
+    multi_stage_tests['Run SDAccel Tests'] = {
         def sdaccel_build_stages = [:]
         String sdaccel_examples_list = 'sdaccel_examples_list.json'
 
@@ -843,4 +846,8 @@ if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
 // SDK Tests
 //=============================================================================
 
-parallel top_parallel_stages
+
+// Run the tests here
+parallel initial_tests
+parallel secondary_tests
+parallel multi_stage_tests

RELEASE_NOTES.md

@@ -26,6 +26,13 @@
          *    1 DDR controller implemented in the SH (always available)
          *    3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
 
+## Release 1.3.6 (See [ERRATA](./ERRATA.md) for unsupported features)
+   *    Simulation model bug fix for transfer size of 64 bytes
+   *    Xilinx 2017.1 Patch AR70350 - fixes report_power hangs.  Patch is automatically applied during setup scripts using MYVIVADO environment variable
+   *    Updated synthesis scripts with -sv option when calling read_verilog
+   *    Added documentation on us-gov-west-1 (GovCloud US)
+   *    Minor EDMA driver fixes and improvements
+
 ## Release 1.3.5 (See [ERRATA](./ERRATA.md) for unsupported features)
    *    [Amazon FPGA Images (AFIs) Tagging](hdk/docs/describe_fpga_images.md) - To help with managing AFIs, you can optionally assign your own metadata to each AFI in the form of tags. Tags are managed using the AWS EC2 CLI commands create-tags, describe-tags and delete-tags.  Tags are custom key/value pairs that can be used to identify or group EC2 resources, including AFIs.  Tags can be used as filters in the describe-fpga-images API to search and filter the AFIs based on the tags you add.
    *    [EDMA driver fixes and improvements](sdk/linux_kernel_drivers/edma/README.md), including polled DMA descriptor completion mode which improves performance on smaller IO (<1MB)

SDAccel/tools/create_sdaccel_afi.sh

@@ -21,7 +21,7 @@ script=${BASH_SOURCE[0]}
 full_script=$(readlink -f $script)
 script_name=$(basename $full_script)
 
-source $AWS_FPGA_REPO_DIR/shared/bin/message_functions.sh
+source $AWS_FPGA_REPO_DIR/shared/bin/set_common_functions.sh
 
 debug=0
 

hdk/cl/examples/README.md

@@ -24,7 +24,7 @@ To install the AWS CLI, please follow the instructions here: (http://docs.aws.am
 
     $ aws configure         # to set your credentials (found in your console.aws.amazon.com page) and default region
 
-Use the aws-cli [region](http://docs.aws.amazon.com/cli/latest/userguide/cli-command-line.html) command line argument to override the profile default region.  Supported regions include: us-east-1, us-west-2 and eu-west-1
+Use the aws-cli [region](http://docs.aws.amazon.com/cli/latest/userguide/cli-command-line.html) command line argument to override the profile default region.  Supported regions include: us-east-1, us-west-2, eu-west-1 and us-gov-west-1.
 
 ### 1. Pick one of the examples and move to its directory
 
@@ -183,7 +183,7 @@ The FPGA Management tools are required to load an AFI onto an FPGA.  Depending o
 ```
 To install the AWS CLI, please follow the instructions here: (http://docs.aws.amazon.com/cli/latest/userguide/installing.html).
 ```
-    $ aws configure         # to set your credentials (found in your console.aws.amazon.com page) and instance region (us-east-1, us-west-2 or eu-west-1)
+    $ aws configure         # to set your credentials (found in your console.aws.amazon.com page) and instance region (us-east-1, us-west-2, eu-west-1 or us-gov-west-1)
 ```
 
 ### 5. Load the AFI

hdk/cl/examples/cl_dram_dma/build/scripts/synth_cl_dram_dma.tcl

@@ -48,7 +48,7 @@ read_verilog -sv [glob $ENC_SRC_DIR/*.?v]
 puts "AWS FPGA: Reading AWS Shell design";
 
 #Read AWS Design files
-read_verilog [ list \
+read_verilog -sv [ list \
   $HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \
   $HDK_SHELL_DESIGN_DIR/lib/bram_2rw.sv \
   $HDK_SHELL_DESIGN_DIR/lib/flop_fifo.sv \

hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma.sv

@@ -22,7 +22,7 @@ module test_dram_dma();
    int timeout_count;
    int fail;
    logic [3:0] status;
-   int         len0 = 128;
+   int         len0 = 64;
    int         len1 = 128;
    int         len2 = 6000;
    int         len3 = 300;

hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl

@@ -48,7 +48,7 @@ read_verilog -sv [glob $ENC_SRC_DIR/*.?v]
 puts "AWS FPGA: Reading AWS Shell design";
 
 #Read AWS Design files
-read_verilog [ list \
+read_verilog -sv [ list \
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sync.v\
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv\
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v\

hdk/cl/examples/cl_hello_world_vhdl/build/scripts/synth_cl_hello_world.tcl

@@ -50,7 +50,7 @@ read_vhdl [ glob $ENC_SRC_DIR/*.vhd ]
 puts "AWS FPGA: Reading AWS Shell design";
 
 #Read AWS Design files
-read_verilog [ list \
+read_verilog -sv [ list \
   $HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \
   $HDK_SHELL_DESIGN_DIR/lib/bram_2rw.sv \
   $HDK_SHELL_DESIGN_DIR/lib/flop_fifo.sv \

hdk/cl/examples/cl_uram_example/build/scripts/synth_cl_uram_example.tcl

@@ -77,7 +77,7 @@ save_bd_design
 puts "AWS FPGA: Reading AWS Shell design";
 
 #Read AWS Design files
-read_verilog [ list \
+read_verilog -sv [ list \
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sync.v\
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv\
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v\

hdk/common/verif/models/sh_bfm/sh_bfm.sv

@@ -2273,10 +2273,13 @@ module sh_bfm #(
    endfunction // start_dma_to_buffer
 
    function bit is_dma_to_cl_done(input int chan);  // 1 = done
+      //$display("In function is_dma_to_cl_done h2c_dma_done is %x \n", h2c_dma_done[chan]);
+      
       return h2c_dma_done[chan];
    endfunction // is_dma_to_cl_done
 
    function bit is_dma_to_buffer_done(input int chan); // 1 = done
+      //$display("In function is_dma_to_buffer_done c2h_dma_done is %x \n", c2h_dma_done[chan]);
       return c2h_dma_done[chan];
    endfunction // is_dma_to_buffer_done
 
@@ -2365,7 +2368,7 @@ module sh_bfm #(
                   num_bytes = last_beat ? (dop.len + dop.cl_addr[5:0])%64 : 64; 
                   axi_data.last = (j == axi_cmd.len) ? 1 : 0;
                   if(num_of_data_beats == 1) begin
-                    num_bytes = (dop.len)%64;
+                    num_bytes = (dop.len == 64) ? 64 : (dop.len)%64;
                     for(int i=start_addr[5:0]; i < (num_bytes+start_addr[5:0]); i++) begin
                       axi_data.data = axi_data.data | tb.hm_get_byte(.addr(dop.buffer + byte_cnt)) << 8*i;
                       axi_data.strb = axi_data.strb | 1 << i;

hdk/hdk_version.txt

@@ -1 +1 @@
-HDK_VERSION=1.3.5
+HDK_VERSION=1.3.6

hdk/supported_vivado_versions.txt

@@ -1,2 +1,3 @@
 Vivado v2017.1_sdx (64-bit)
 Vivado v2017.1_sdxop (64-bit)
+Vivado v2017.1_sdx_AR70350 (64-bit)

hdk_setup.sh

@@ -28,8 +28,6 @@ script_name=$(basename $full_script)
 script_dir=$(dirname $full_script)
 current_dir=$(pwd)
 
-source $script_dir/shared/bin/message_functions.sh
-
 debug=0
 
 # This function checks if an environment module exists
@@ -82,7 +80,7 @@ for (( i = 0; i < ${#args[@]}; i++ )); do
   esac
 done
 
-source $script_dir/shared/bin/set_AWS_FPGA_REPO_DIR.sh
+source $script_dir/shared/bin/set_common_functions.sh
 source $script_dir/shared/bin/set_common_env_vars.sh
 
 hdk_shell_version=$(readlink $HDK_COMMON_DIR/shell_stable)
@@ -238,4 +236,8 @@ else
 fi
 
 cd $current_dir
+
+# Install any patches as required
+setup_patches
+
 info_msg "AWS HDK setup PASSED.";

sdaccel_setup.sh

@@ -27,10 +27,7 @@ script_name=$(basename $full_script)
 script_dir=$(dirname $full_script)
 current_dir=$(pwd)
 
-source $script_dir/shared/bin/message_functions.sh
-
-source $script_dir/shared/bin/set_AWS_FPGA_REPO_DIR.sh
-
+source $script_dir/shared/bin/set_common_functions.sh
 source $script_dir/shared/bin/set_common_env_vars.sh
 
 # Source sdk_setup.sh
@@ -281,6 +278,10 @@ info_msg "The default AWS Platform has been set to: \"AWS_PLATFORM=\$AWS_PLATFOR
 info_msg "To change the platform for 1DDR:  \"export AWS_PLATFORM=\$AWS_PLATFORM_1DDR\" "
 info_msg "To change the platform for 4DDR Debug:  \"export AWS_PLATFORM=\$AWS_PLATFORM_4DDR_DEBUG\" "
 
+# Install patches as required.
+
+setup_patches
+
 cd $current_dir
 
 info_msg "SDAccel Setup PASSED"

sdk/linux_kernel_drivers/edma/Makefile

@@ -19,7 +19,9 @@ edma-drv-objs :=  \
 KERNEL_VERSION ?= $(shell uname -r)
 
 KBUILD_CPPFLAGS+=-I$(PWD)/
-KBUILD_CPPFLAGS+=-DDRV_MODULE_VERSION=\"alpha1\"
+KBUILD_CPPFLAGS+=-DDRV_MODULE_VERSION=\"1.0.0\"
+
+INSTALLED_MOD_NAME=edma-drv
 
 ifeq ($(BACKEND_MEMORY),1)
         KBUILD_CPPFLAGS+=-DBACKEND_MEMORY=1
@@ -37,3 +39,13 @@ unit-test:
 	make -C ./unit-test all
 clean:
 	make -C /lib/modules/$(KERNEL_VERSION)/build M=$(PWD) clean
+
+install:
+	echo $(INSTALLED_MOD_NAME) > /etc/modules-load.d/$(INSTALLED_MOD_NAME).conf
+	cp edma-drv.ko /lib/modules/`uname -r`/$(INSTALLED_MOD_NAME).ko
+	depmod
+
+uninstall:
+	rm -f /etc/modules-load.d/$(INSTALLED_MOD_NAME).conf
+	rm -f /lib/modules/`uname -r`/$(INSTALLED_MOD_NAME).ko
+	depmod

sdk/linux_kernel_drivers/edma/edma.c

@@ -35,8 +35,8 @@
 #include "edma_dev.h"
 #include "edma_backend.h"
 
-MODULE_AUTHOR("Alex Levin <levinale@amazon.com>");
-MODULE_DESCRIPTION("Amazon EDMA driver");
+MODULE_AUTHOR("Amazon.com, Inc. or its affiliates");
+MODULE_DESCRIPTION("Elastic Direct Memory Access");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_MODULE_VERSION);
 

sdk/linux_kernel_drivers/edma/edma_dev.c

@@ -88,7 +88,7 @@ MODULE_PARM_DESC(single_transaction_size, "The size of a single transaction over
 
 unsigned int edma_queue_depth = 1024;
 module_param(edma_queue_depth, uint, 0);
-MODULE_PARM_DESC(ebcs_queue_depth, "EDMA queue depth. (default=1024)");
+MODULE_PARM_DESC(edma_queue_depth, "EDMA queue depth. (default=1024)");
 
 static unsigned int fsync_timeout_sec = 9;
 module_param(fsync_timeout_sec, uint, 0);