Library: power, UART, I2C, RS232 components...

src/faebryk/core/module.py

@@ -4,7 +4,7 @@
 from typing import TYPE_CHECKING, Callable, Iterable
 
 from faebryk.core.moduleinterface import GraphInterfaceModuleSibling
-from faebryk.core.node import Node, f_field
+from faebryk.core.node import Node, NodeException, f_field
 from faebryk.core.trait import Trait
 from faebryk.libs.util import unique_ref
 
@@ -14,6 +14,12 @@
 logger = logging.getLogger(__name__)
 
 
+class ModuleException(NodeException):
+    def __init__(self, module: "Module", *args: object) -> None:
+        self.module = module
+        super().__init__(module, *args)
+
+
 class Module(Node):
     class TraitT(Trait): ...
 

src/faebryk/exporters/parameters/parameters_to_file.py

@@ -22,39 +22,37 @@ def export_parameters_to_file(module: Module, path: Path):
         ]
 
     logger.info(f"Writing parameters to {path}")
+    out = ""
     if path.suffix == ".txt":
-        with open(path, "w") as f:
-            for module_name, paras in sorted(parameters.items()):
-                if paras:
-                    f.write(f"{module_name}\n")
-                    f.writelines(
-                        [
-                            f"    {par_name}: {par_value}\n"
-                            for par_dict in paras
-                            for par_name, par_value in par_dict.items()
-                        ]
-                    )
-                    f.write("\n")
-            f.close()
+        for module_name, paras in sorted(parameters.items()):
+            if paras:
+                out += f"{module_name}\n"
+                out += "\n".join(
+                    [
+                        f"    {par_name}: {par_value}\n"
+                        for par_dict in paras
+                        for par_name, par_value in par_dict.items()
+                    ]
+                )
+                out += "\n"
     elif path.suffix == ".md":
-        with open(path, "w") as f:
-            f.write("# Module Parameters\n")
-            for module_name, paras in sorted(parameters.items()):
-                if paras:
-                    f.write(f"**{module_name.replace("|","|")}**\n")
-                    f.write("| Parameter Name | Parameter Value |\n")
-                    f.write("| --- | --- |\n")
-                    f.writelines(
-                        [
-                            f"| {par_name.replace("|","|")} | {str(par_value).replace("|","|")} |\n"  # noqa E501
-                            for par_dict in paras
-                            for par_name, par_value in par_dict.items()
-                        ]
-                    )
-                    f.write("\n")
-            f.write("\n")
-            f.close()
+        out += "# Module Parameters\n"
+        for module_name, paras in sorted(parameters.items()):
+            if paras:
+                out += f"**{module_name.replace("|","|")}**\n"
+                out += "| Parameter Name | Parameter Value |\n"
+                out += "| --- | --- |\n"
+                out += "\n".join(
+                    [
+                        f"| {par_name.replace("|","|")} | {str(par_value).replace("|","|")} |\n"  # noqa E501
+                        for par_dict in paras
+                        for par_name, par_value in par_dict.items()
+                    ]
+                )
+                out += "\n"
     else:
         AssertionError(
             f"Export to file extension [{path.suffix}] not supported in {path}"
         )
+
+    path.write_text(out)

src/faebryk/library/B0505S_1WR3.py

@@ -0,0 +1,71 @@
+# This file is part of the faebryk project
+# SPDX-License-Identifier: MIT
+
+import logging
+
+import faebryk.library._F as F  # noqa: F401
+from faebryk.core.module import Module
+from faebryk.libs.library import L  # noqa: F401
+from faebryk.libs.picker.picker import DescriptiveProperties
+from faebryk.libs.units import P  # noqa: F401
+
+logger = logging.getLogger(__name__)
+
+
+class B0505S_1WR3(Module):
+    """
+    Isolated 5V DC to 5V DC converter.
+    R suffix is for shortcircuit protection
+    """
+
+    # ----------------------------------------
+    #     modules, interfaces, parameters
+    # ----------------------------------------
+    power_in: F.ElectricPower
+    power_out: F.ElectricPower
+
+    # ----------------------------------------
+    #                 traits
+    # ----------------------------------------
+    designator_prefix = L.f_field(F.has_designator_prefix_defined)("U")
+
+    datasheet = L.f_field(F.has_datasheet_defined)(
+        "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2307211806_EVISUN-B0505S-1WR3_C7465178.pdf"
+    )
+
+    @L.rt_field
+    def can_attach_to_footprint(self):
+        return F.can_attach_to_footprint_via_pinmap(
+            pinmap={
+                "1": self.power_in.lv,
+                "2": self.power_in.hv,
+                "3": self.power_out.lv,
+                "4": self.power_out.hv,
+            }
+        )
+
+    @L.rt_field
+    def has_descriptive_properties_defined(self):
+        return F.has_descriptive_properties_defined(
+            {
+                DescriptiveProperties.partno: "B0505S-1WR3",
+            },
+        )
+
+    # self.add_trait(can_bridge_defined(self.power_in, self.power_out))
+    def __preinit__(self):
+        # ----------------------------------------
+        #            parametrization
+        # ----------------------------------------
+        self.power_in.get_trait(F.can_be_decoupled).decouple().capacitance.merge(
+            F.Range.from_center_rel(4.7 * P.uF, 0.1)
+        )
+        self.power_out.get_trait(F.can_be_decoupled).decouple().capacitance.merge(
+            F.Range.from_center_rel(10 * P.uF, 0.1)
+        )
+
+        # ----------------------------------------
+        #              connections
+        # ----------------------------------------
+        self.power_in.voltage.merge(F.Range(4.3 * P.V, 9 * P.V))
+        self.power_out.voltage.merge(F.Range.from_center(5 * P.V, 0.5 * P.V))

src/faebryk/library/Button.py

@@ -15,7 +15,9 @@ class Button(Module):
     unnamed = L.list_field(2, F.Electrical)
     height: F.TBD[Quantity]
 
-    designator_prefix = L.f_field(F.has_designator_prefix_defined)("SW")
+    designator_prefix = L.f_field(F.has_designator_prefix_defined)(
+        F.has_designator_prefix.Prefix.S
+    )
 
     @L.rt_field
     def can_bridge(self):

src/faebryk/library/CBM9002A_56ILG_Reference_Design.py → src/faebryk/library/CBM9002A_56ILG_ReferenceDesign.py

@@ -7,7 +7,7 @@
 from faebryk.libs.units import P
 
 
-class CBM9002A_56ILG_Reference_Design(Module):
+class CBM9002A_56ILG_ReferenceDesign(Module):
     """
     Minimal working example for the CBM9002A_56ILG
     """
@@ -82,5 +82,5 @@ def __preinit__(self):
             F.Range.from_center_rel(24 * P.Mhertz, 0.05)
         )
         self.oscillator.crystal.frequency_tolerance.merge(
-            F.Range.upper_bound(20 * P.ppm)
+            F.Range(0 * P.ppm, 20 * P.ppm)
         )

src/faebryk/library/CH342.py

@@ -0,0 +1,136 @@
+# This file is part of the faebryk project
+# SPDX-License-Identifier: MIT
+
+import logging
+from enum import Enum, auto
+
+import faebryk.library._F as F  # noqa: F401
+from faebryk.core.module import Module, ModuleException
+from faebryk.libs.library import L  # noqa: F401
+from faebryk.libs.units import P
+from faebryk.libs.util import assert_once
+
+logger = logging.getLogger(__name__)
+
+
+class CH342(Module):
+    """
+    Base class for CH342x USB to double UART converter
+    """
+
+    class IntegratedLDO(Module):
+        power_in: F.ElectricPower
+        power_out: F.ElectricPower
+
+        def __preinit__(self):
+            F.ElectricLogic.connect_all_module_references(self, gnd_only=True)
+
+            self.power_out.voltage.merge(F.Range.from_center(3.3 * P.V, 0.3 * P.V))
+            self.power_in.voltage.merge(F.Range(4 * P.V, 5.5 * P.V))
+
+        @L.rt_field
+        def bridge(self):
+            return F.can_bridge_defined(self.power_in, self.power_out)
+
+    class IOPowerConfiguration(Enum):
+        USB_5V = auto()
+        """IO powered by USB 5V"""
+        INTERNAL_3V3 = auto()
+        """IO powered by the integrated 3.3V regulator"""
+        EXTERNAL = auto()
+        """IO powered by an external 1.8V-5V source"""
+
+    class ChipPowerConfiguration(Enum):
+        USB_5V = auto()
+        """Chip powered by USB 5V"""
+        EXTERNAL_5V = auto()
+        """Chip powered by an external 5V source"""
+        EXTERNAL_3V3 = auto()
+        """Chip powered by an external 3.3V source"""
+
+    @assert_once
+    def set_power_configuration(
+        self,
+        chip_power_configuration: ChipPowerConfiguration = ChipPowerConfiguration.USB_5V,  # noqa: E501
+        io_voltage_configuration: IOPowerConfiguration = IOPowerConfiguration.INTERNAL_3V3,  # noqa: E501
+    ):
+        """Configure how the chip is powered, and what the io voltage will be."""
+        # how is the chip powered
+        if chip_power_configuration == self.ChipPowerConfiguration.EXTERNAL_3V3:
+            # short the integrated regulator power input to the output to disable
+            self.integrated_regulator.power_in.connect(self.power_3v)
+        elif chip_power_configuration == self.ChipPowerConfiguration.USB_5V:
+            # use the USB power to power the chip
+            self.usb.usb_if.buspower.connect(self.integrated_regulator.power_in)
+        else:
+            # use an external 5V power source for the chip
+            ...
+
+        # how is the IO powered
+        if io_voltage_configuration == self.IOPowerConfiguration.INTERNAL_3V3:
+            # check if the integrated regulator is not disabled
+            if chip_power_configuration == self.ChipPowerConfiguration.EXTERNAL_3V3:
+                raise ModuleException(
+                    self,
+                    "Cannot power IO from the integrated regulator when it is disabled, use 'EXTERNAL' power configuration instead",  # noqa: E501
+                )
+            # io is 3v3 and powered by the integrated regulator (10mA max)
+            self.power_io.connect(self.power_3v)
+            F.ElectricLogic.connect_all_module_references(
+                self,
+                exclude={
+                    self.integrated_regulator.power_in,
+                },
+            )
+        elif io_voltage_configuration == self.IOPowerConfiguration.USB_5V:
+            # io is 5v and powered by USB
+            self.power_io.connect(self.usb.usb_if.buspower)
+            F.ElectricLogic.connect_all_module_references(
+                self,
+                exclude={
+                    self.integrated_regulator.power_in,
+                    self.integrated_regulator.power_out,
+                    self.power_3v,
+                },
+            )
+        else:
+            # io is 1.8V-5V and powered by an external source
+            ...
+
+    # ----------------------------------------
+    #     modules, interfaces, parameters
+    # ----------------------------------------
+    usb: F.USB2_0
+    # uart_base = L.list_field(2, F.UART_Base)
+
+    integrated_regulator: IntegratedLDO
+    power_io: F.ElectricPower
+    power_3v: F.ElectricPower
+
+    # ----------------------------------------
+    #                 traits
+    # ----------------------------------------
+    datasheet = L.f_field(F.has_datasheet_defined)(
+        "https://wch-ic.com/downloads/CH342DS1_PDF.html"
+    )
+    designator_prefix = L.f_field(F.has_designator_prefix_defined)(
+        F.has_designator_prefix.Prefix.U
+    )
+
+    def __preinit__(self):
+        # ----------------------------------------
+        #                aliasess
+        # ----------------------------------------
+        # ----------------------------------------
+        #            parametrization
+        # ----------------------------------------
+        self.power_3v.voltage.merge(F.Range.from_center(3.3 * P.V, 0.3 * P.V))
+        self.power_io.voltage.merge(F.Range(1.7 * P.V, 5.5 * P.V))
+
+        # ----------------------------------------
+        #              connections
+        # ----------------------------------------
+        F.ElectricLogic.connect_all_module_references(self, gnd_only=True)
+
+        # chip internal connection
+        self.integrated_regulator.power_out.connect(self.power_3v)