Fix: comply with most of fabll code guidelines

src/faebryk/library/B0505S_1WR3.py

@@ -44,28 +44,28 @@ def can_attach_to_footprint(self):
             }
         )
 
+    @L.rt_field
+    def has_descriptive_properties_defined(self):
+        return F.has_descriptive_properties_defined(
+            {
+                DescriptiveProperties.partno: "B0505S-1WR3",
+            },
+        )
+
     # self.add_trait(can_bridge_defined(self.power_in, self.power_out))
     def __preinit__(self):
         # ----------------------------------------
         #            parametrization
         # ----------------------------------------
         self.power_in.get_trait(F.can_be_decoupled).decouple().capacitance.merge(
-            F.Constant(4.7 * P.uF)
+            4.7 * P.uF
         )
         self.power_out.get_trait(F.can_be_decoupled).decouple().capacitance.merge(
-            F.Constant(10 * P.uF)
+            10 * P.uF
         )
 
         # ----------------------------------------
         #              connections
         # ----------------------------------------
         self.power_in.voltage.merge(F.Range(4.3 * P.V, 9 * P.V))
         self.power_out.voltage.merge(F.Range.from_center(5 * P.V, 0.5 * P.V))
-
-        self.add(
-            F.has_descriptive_properties_defined(
-                {
-                    DescriptiveProperties.partno: "B0505S-1WR3",
-                },
-            )
-        )

src/faebryk/library/CBM9002A_56ILG_Reference_Design.py → src/faebryk/library/CBM9002A_56ILG_ReferenceDesign.py

@@ -7,7 +7,7 @@
 from faebryk.libs.units import P
 
 
-class CBM9002A_56ILG_Reference_Design(Module):
+class CBM9002A_56ILG_ReferenceDesign(Module):
     """
     Minimal working example for the CBM9002A_56ILG
     """

src/faebryk/library/CH342.py

@@ -44,21 +44,23 @@ class DuplexMode(Enum):
         "https://wch-ic.com/downloads/CH342DS1_PDF.html"
     )
 
+    @L.rt_field
+    def single_electric_reference(self):
+        return F.has_single_electric_reference_defined(
+            F.ElectricLogic.connect_all_module_references(self, gnd_only=True)
+        )
+
     def __preinit__(self):
         # ----------------------------------------
         #                aliasess
         # ----------------------------------------
-        gnd = self.usb.usb_if.buspower.lv
-
         # ----------------------------------------
         #            parametrization
         # ----------------------------------------
         self.vdd_5v.voltage.merge(F.Range(4 * P.V, 5.5 * P.V))
-        self.v_3v.voltage.merge(F.Constant(3.3 * P.V))
+        self.v_3v.voltage.merge(3.3 * P.V)
         self.v_io.voltage.merge(F.Range(1.7 * P.V, 3.6 * P.V))
 
         # ----------------------------------------
         #              connections
         # ----------------------------------------
-        for powerrail in [self.vdd_5v, self.v_io, self.v_3v]:
-            powerrail.lv.connect(gnd)

src/faebryk/library/CH342F.py

@@ -76,6 +76,15 @@ def can_attach_to_footprint(self):
             }
         )
 
+    @L.rt_field
+    def descriptive_properties(self):
+        return F.has_descriptive_properties_defined(
+            {
+                DescriptiveProperties.manufacturer: "WCH",
+                DescriptiveProperties.partno: "CH342F",
+            },
+        )
+
     def __init__(
         self,
         duplex_mode_uart_0: F.CH342.DuplexMode = F.CH342.DuplexMode.FULL,
@@ -93,21 +102,21 @@ def __preinit__(self) -> None:
         #            parametrization
         # ----------------------------------------
         self.vdd_5v.voltage.merge(F.Range(4 * P.V, 5.5 * P.V))
-        self.v_3v.voltage.merge(F.Constant(3.3 * P.V))
+        self.v_3v.voltage.merge(3.3 * P.V)
         self.v_io.voltage.merge(F.Range(1.7 * P.V, 3.6 * P.V))
 
         # set the duplex mode
         if self._duplex_mode_uart_0 == F.CH342.DuplexMode.HALF:
             self.uart[0].dtr.get_trait(F.ElectricLogic.can_be_pulled).pull(up=False)
             NotNone(
                 self.uart[0].dtr.get_trait(F.ElectricLogic.has_pulls).get_pulls()[1]
-            ).resistance.merge(F.Constant(4.7 * P.kohm))
+            ).resistance.merge(4.7 * P.kohm)
             self.tnow[0].connect(self.uart[0].dtr)
         if self._duplex_mode_uart_1 == F.CH342.DuplexMode.HALF:
             self.uart[1].dtr.get_trait(F.ElectricLogic.can_be_pulled).pull(up=False)
             NotNone(
                 self.uart[1].dtr.get_trait(F.ElectricLogic.has_pulls).get_pulls()[1]
-            ).resistance.merge(F.Constant(4.7 * P.kohm))
+            ).resistance.merge(4.7 * P.kohm)
             self.tnow[1].connect(self.uart[1].dtr)
 
         # ----------------------------------------
@@ -117,15 +126,9 @@ def __preinit__(self) -> None:
         self.vdd_5v.connect(self.usb.usb_if.buspower)
         self.v_3v.connect(self.v_io)
 
-        self.vdd_5v.get_trait(F.can_be_decoupled).decouple().capacitance.merge(
-            F.Constant(1 * P.uF)
-        )
-        self.v_3v.get_trait(F.can_be_decoupled).decouple().capacitance.merge(
-            F.Constant(0.1 * P.uF)
-        )
-        self.v_io.get_trait(F.can_be_decoupled).decouple().capacitance.merge(
-            F.Constant(1 * P.uF)
-        )
+        self.vdd_5v.get_trait(F.can_be_decoupled).decouple().capacitance.merge(1 * P.uF)
+        self.v_3v.get_trait(F.can_be_decoupled).decouple().capacitance.merge(0.1 * P.uF)
+        self.v_io.get_trait(F.can_be_decoupled).decouple().capacitance.merge(1 * P.uF)
 
         F.can_attach_to_footprint().attach(
             F.QFN(
@@ -137,12 +140,3 @@ def __preinit__(self) -> None:
                 has_thermal_vias=False,
             )
         )
-
-        self.add(
-            F.has_descriptive_properties_defined(
-                {
-                    DescriptiveProperties.manufacturer: "WCH",
-                    DescriptiveProperties.partno: "CH342F",
-                },
-            )
-        )

src/faebryk/library/CH344Q.py

@@ -60,6 +60,15 @@ def enable_hardware_flow_conrol(self):
     # ----------------------------------------
     #                 traits
     # ----------------------------------------
+    @L.rt_field
+    def descriptive_properties(self):
+        return F.has_descriptive_properties_defined(
+            {
+                DescriptiveProperties.manufacturer: "WCH",
+                DescriptiveProperties.partno: "CH344Q",
+            },
+        )
+
     @L.rt_field
     def can_attach_to_footprint(self):
         return F.can_attach_to_footprint_via_pinmap(
@@ -124,11 +133,3 @@ def __preinit__(self):
         # ------------------------------------
         #          parametrization
         # ------------------------------------
-        self.add(
-            F.has_descriptive_properties_defined(
-                {
-                    DescriptiveProperties.manufacturer: "WCH",
-                    DescriptiveProperties.partno: "CH344Q",
-                },
-            )
-        )

src/faebryk/library/DE9Connector.py

@@ -19,7 +19,7 @@ class DE9Connector(Module):
     # ----------------------------------------
     #     modules, interfaces, parameters
     # ----------------------------------------
-    unnamed = L.list_field(9, F.Electrical)
+    contact = L.list_field(9, F.Electrical)
     shield: F.Electrical
 
     # ----------------------------------------

src/faebryk/library/DE9RS232Connector.py

@@ -4,46 +4,55 @@
 import logging
 
 import faebryk.library._F as F  # noqa: F401
+from faebryk.core.module import Module
 from faebryk.libs.library import L  # noqa: F401
 from faebryk.libs.units import P  # noqa: F401
 
 logger = logging.getLogger(__name__)
 
 
-class DE9RS232Connector(F.DE9Connector):
+class DE9RS232Connector(Module):
     """
     Standard RS232 bus on DE-9 connector
     """
 
     # ----------------------------------------
     #     modules, interfaces, parameters
     # ----------------------------------------
+    connector: F.DE9Connector
     rs232: F.RS232
-    signal_gnd: F.Electrical
 
     # ----------------------------------------
     #                 traits
     # ----------------------------------------
     @L.rt_field
     def can_attach_to_footprint(self):
-        pinmap = {f"{i+1}": ei for i, ei in enumerate(self.unnamed)}
-        pinmap.update({"10": self.shield})
+        pinmap = {f"{i+1}": ei for i, ei in enumerate(self.connector.contact)}
+        pinmap.update({"10": self.connector.shield})
         return F.can_attach_to_footprint_via_pinmap(pinmap)
 
+    @L.rt_field
+    def single_electric_reference(self):
+        return F.has_single_electric_reference_defined(
+            F.ElectricLogic.connect_all_module_references(self)
+        )
+
     def __preinit__(self):
         # ------------------------------------
         #           connections
         # ------------------------------------
-        self.rs232.tx.signal.connect(self.unnamed[2])
-        self.rs232.rx.signal.connect(self.unnamed[1])
-        self.rs232.dtr.signal.connect(self.unnamed[3])
-        self.rs232.dcd.signal.connect(self.unnamed[0])
-        self.rs232.dsr.signal.connect(self.unnamed[5])
-        self.rs232.ri.signal.connect(self.unnamed[8])
-        self.rs232.rts.signal.connect(self.unnamed[6])
-        self.rs232.cts.signal.connect(self.unnamed[7])
-
-        self.signal_gnd.connect(self.unnamed[4])
+        self.rs232.tx.signal.connect(self.connector.contact[2])
+        self.rs232.rx.signal.connect(self.connector.contact[1])
+        self.rs232.dtr.signal.connect(self.connector.contact[3])
+        self.rs232.dcd.signal.connect(self.connector.contact[0])
+        self.rs232.dsr.signal.connect(self.connector.contact[5])
+        self.rs232.ri.signal.connect(self.connector.contact[8])
+        self.rs232.rts.signal.connect(self.connector.contact[6])
+        self.rs232.cts.signal.connect(self.connector.contact[7])
+
+        self.rs232.get_trait(
+            F.has_single_electric_reference
+        ).get_reference().lv.connect(self.connector.contact[4])
 
         # ------------------------------------
         #          parametrization

src/faebryk/library/ESP32_C3_MINI_1_Reference_Design.py → src/faebryk/library/ESP32_C3_MINI_1_ReferenceDesign.py

@@ -10,7 +10,7 @@
 logger = logging.getLogger(__name__)
 
 
-class ESP32_C3_MINI_1_Reference_Design(Module):
+class ESP32_C3_MINI_1_ReferenceDesign(Module):
     """ESP32_C3_MINI_1 Module reference design"""
 
     esp32_c3_mini_1: F.ESP32_C3_MINI_1

src/faebryk/library/ISO1540.py

@@ -33,6 +33,15 @@ class ISO1540(Module):
     )
     designator_prefix = L.f_field(F.has_designator_prefix_defined)("U")
 
+    @L.rt_field
+    def descriptive_properties(self):
+        return F.has_descriptive_properties_defined(
+            {
+                DescriptiveProperties.manufacturer: "Texas Instruments",
+                DescriptiveProperties.partno: "ISO1540DR",
+            },
+        )
+
     @L.rt_field
     def can_attach_to_footprint(self):
         return F.can_attach_to_footprint_via_pinmap(
@@ -61,12 +70,3 @@ def __preinit__(self):
 
         self.power.decoupled.decouple().capacitance.merge(10 * P.uF)
         self.power_iso.decoupled.decouple().capacitance.merge(10 * P.uF)
-
-        self.add(
-            F.has_descriptive_properties_defined(
-                {
-                    DescriptiveProperties.manufacturer: "Texas Instruments",
-                    DescriptiveProperties.partno: "ISO1540DR",
-                },
-            )
-        )

src/faebryk/library/RP2040_Reference_Design.py → src/faebryk/library/RP2040_ReferenceDesign.py

@@ -12,7 +12,7 @@
 logger = logging.getLogger(__name__)
 
 
-class RP2040_Reference_Design(Module):
+class RP2040_ReferenceDesign(Module):
     """Minimal required design for the Raspberry Pi RP2040 microcontroller.
     Based on the official Raspberry Pi RP2040 hardware design guidlines"""
 

src/faebryk/library/SP3243E.py

@@ -19,11 +19,16 @@ class SP3243E(F.RS232_3D5R_Tranceiver):
     # ----------------------------------------
     #     modules, interfaces, parameters
     # ----------------------------------------
-    c1: F.ElectricPower
-    c2: F.ElectricPower
-    vp: F.ElectricPower
-    vn: F.ElectricPower
+    voltage_doubler_charge_pump_power: F.ElectricPower
+    """Terminal of the voltage doubler charge-pump capacitor """
+    inverting_charge_pump_power: F.ElectricPower
+    """Terminal of the inverting charge-pump capacitor """
+    positive_charge_pump_power: F.ElectricPower
+    """Regulated +5.5V output generated by the charge pump """
+    negative_charge_pump_power: F.ElectricPower
+    """Regulated -5.5V output generated by the charge pump """
     power: F.ElectricPower
+    """Power input to the module"""
 
     enable: F.ElectricLogic
     online: F.ElectricLogic
@@ -37,6 +42,15 @@ class SP3243E(F.RS232_3D5R_Tranceiver):
         "https://assets.maxlinear.com/web/documents/sp3243e.pdf"
     )
 
+    @L.rt_field
+    def descriptive_properties(self):
+        return F.has_descriptive_properties_defined(
+            {
+                DescriptiveProperties.manufacturer: "MaxLinear",
+                DescriptiveProperties.partno: "SP3243EBEA-L/TR",
+            },
+        )
+
     def __preinit__(self):
         # ------------------------------------
         #           connections
@@ -56,12 +70,3 @@ def __preinit__(self):
         #          parametrization
         # ------------------------------------
         self.power.voltage.merge(F.Range(3.0 * P.V, 5.5 * P.V))
-
-        self.add(
-            F.has_descriptive_properties_defined(
-                {
-                    DescriptiveProperties.manufacturer: "MaxLinear",
-                    DescriptiveProperties.partno: "SP3243EBEA-L/TR",
-                },
-            )
-        )

src/faebryk/library/TPS2116.py

@@ -15,6 +15,9 @@ class TPS2116(F.PowerMux):
     2to1 1.6 V to 5.5 V, 2.5-A Low IQ Power Mux with Manual and Priority Switchover
     """
 
+    # ----------------------------------------
+    #     modules, interfaces, parameters
+    # ----------------------------------------
     power_in = L.list_field(2, F.ElectricPower)
     power_out: F.ElectricPower
     select: F.Electrical
@@ -37,8 +40,14 @@ def single_electric_reference(self):
         )
 
     def __preinit__(self):
-        gnd = self.power_out.lv
-
+        # ------------------------------------
+        #           connections
+        # ------------------------------------
+        self.power_in[0].connect_shallow(self.power_out)
+        self.power_in[1].connect_shallow(self.power_out)
+
+        # ------------------------------------
+        #          parametrization
+        # ------------------------------------
         for power in [self.power_in[0], self.power_in[1], self.power_out]:
             power.voltage.merge(F.Range(1.6 * P.V, 5.5 * P.V))
-            power.lv.connect(gnd)