Ci test #34
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added 30 commits
February 2, 2022 10:32
This adds support for the RTL9300 and RTL9310 I2C controller. The controller implements the SMBus protocol for SMBus transfers over an I2C bus. The driver supports selecting one of the 2 possible SCL pins and any of the 8 possible SDA pins. Bus speeds of 100kHz (standard speed) and 400kHz (high speed I2C) are supported. Signed-off-by: Birger Koblitz <[email protected]>
The RTL9300/RTL9310 I2C controllers have support for 2 independent I2C masters, each with a fixed SCL pin, that cannot be changed. Each of these masters can use 8 (RTL9300) or 16 (RTL9310) different pins for SDA. This multiplexer directly controls the two masters and their shared IO configuration registers to allow multiplexing between any of these busses. The two masters cannot be used in parallel as the multiplex is protected by a standard multiplex lock. Signed-off-by: Birger Koblitz <[email protected]>
The EEPROMs on SFP modules are compatible both to I2C as well as SMBus. However, the kernel so far only supports I2C access. We add SMBus access routines, because the I2C driver for the RTL9300 HW only supports that protocol. At the same time we disable I2C access to PHYs on SFP modules as otherwise detection of any SFP module would fail. This is not in any way problematic at this point in time since the RTL93XX platform so far does not support PHYs on SFP modules. An alternative is to implement PHY over SMBus access, see e.g. the link below. The patch is inspired by the work here: https://bootlin.com/blog/sfp-modules-on-a-board-running-linux/ Signed-off-by: Birger Koblitz <[email protected]>
mv generic/target.mk to rtl838x/target.mk in order to create an initial makefile for the rtl838x sub-architecture Signed-off-by: Birger Koblitz <[email protected]>
This defines the sub-target specific properties for the RTL838X sub-target. Signed-off-by: Birger Koblitz <[email protected]>
Adds the initial Makefile for the RTL839x sub-architecture. Signed-off-by: Birger Koblitz <[email protected]>
Move the generic kernel configs to the rtl838x sub-target. Signed-off-by: Birger Koblitz <[email protected]>
Create the RTL838x specific Makefiles. Move CPU-type into rtl838x.mk as this is specifc to that platform. Add rtl838x subtarget into main Makefile. Signed-off-by: Birger Koblitz <[email protected]>
Creates RTL83XX as a basic kernel config parameter for the RTL838X, RTL839x, RTL930X and RTL931X platforms with respective configurations for the SoCs, which are introduced in addition. Signed-off-by: Birger Koblitz <[email protected]>
The RTL838X SoCs do not use Aquantia PHYs, remove this. Also the RTL838X uses a high resolution R4K timer. Signed-off-by: Birger Koblitz <[email protected]>
In order for the Platform includes to be available on all sub-targets, make them dependent on CONFIG_RTL83XX. Signed-off-by: Birger Koblitz <[email protected]>
Adds Multithreading support functions in prom.c. Signed-off-by: Birger Koblitz <[email protected]>
Adds a dedicated kernel configuration for RTL839X SoCs enabling SMP. Signed-off-by: Birger Koblitz <[email protected]>
In order to support VSMP, enable support for both VPEs of the RTL839X and RTL930X SoCs in the irq-realtek-rtl driver. Add support for IRQ affinity setting. We move the driver out of the upstream patch into a dedicated file in order not to patch the patch. Signed-off-by: Birger Koblitz <[email protected]>
Replace the interrupt controller node with the new realtek,rtl-intc node and change all device interrupts to use the 2 field notation: interrupts = <[SoC IRQ] [Index to MIPS IRQ]> Signed-off-by: Birger Koblitz <[email protected]>
…ller Update the IRQ configuration to work with the new rtl-intc controller. Also change all KSEG1 addresses in reg = <> of the devics to physical addresses. Signed-off-by: Birger Koblitz <[email protected]>
The GS1900-48 is a 48 + 2 port Gigabit L2 switch with 48 gigabit ports.
Hardware:
RTL8393M SoC
Macronix MX25l12805D (16MB flash)
128MB RAM
6 * RTL8218B external PHY
2 * RTL8231 GPIO extenders to control the port LEDs, system LED and
Reset button
2 Uplink ports are SFP cages which support 1000 Base-X mini GBIC modules.
Power is supplied via a 230 volt mains connector.
The board has a hard reset switch SW1, which is is not reachable from the outside.
J4 provides a 12V RS232 serial connector which is connected through U8 to
the 3.3V UART of the RTL8393. Conversion is done by U8, a SIPEX 3232EC.
To connect to the UART, wires can be soldered to R603 (TX) and R602 (RX).
Installation:
Install the squashfs image via Realtek's original Web-Interface.
Signed-off-by: Birger Koblitz <[email protected]>
Set CONFIG_FORCE_MAX_ZONEORDER setting to 13 to allow larger contiguous memory allocation for the DMA of the Ethernet driver. Increase the number of entries in the RX ring to 300. Signed-off-by: Birger Koblitz <[email protected]>
Setting bits 20 and 23 in a u16 is obviously wrong. According to https://www.svanheule.net/realtek/cypress/cputag cpu_tag[2] starts at bit 48 in the cpu-tag structure, so bit 43 is bit 5 in cpu_tag[2] and bit 40 is bit 8 in cpu_tag[2]. Signed-off-by: Birger Koblitz <[email protected]>
Rename the SoC-specific rtl838x_reg structure in the Ethernet driver to avoid confusion with the structure of the same name in the DSA driver. New name is: rtl838x_eth_reg Signed-off-by: Birger Koblitz <[email protected]>
Fix the update counter of the RX ring, add SDS access functions for RTL931X. Signed-off-by: Birger Koblitz <[email protected]>
Adds RTL931X SerDes access functions as needed by the Ethernet driver. Signed-off-by: Birger Koblitz <[email protected]>
Correct offset in RX tag structure. Correct offload decision flagging. Signed-off-by: Birger Koblitz <[email protected]>
Do not lock the register structure in IRQ context. It is not necessary and leads to lockups under SMP load. Signed-off-by: Birger Koblitz <[email protected]>
Various fixes to enable Ethernet on the RTL931X: - Network start and stop sequence for RTL931X HW - MDIO access on RTL931X SoC - Chip initialization - SerDes setup Signed-off-by: Birger Koblitz <[email protected]>
The RTL9300 has a broken R4K MIPS timer interrupt, however, the R4K clocksource works. We replace the RTL9300 timer with a Clock Event Timer (CEVT), which is VSMP aware and can be instantiated as part of brining a VSMTP cpu up instead of the R4K CEVT source. For this we place the RTL9300 CEVT timer in arch/mips/kernel together with other MIPS CEVT timers, initialize the SoC IRQs from a modified smp-mt.c and instantiate each timer as part of the MIPS time setup in arch/mips/include/asm/time.h instead of the R4K CEVT, similarly as is done by other MIPS CEVT timers. Signed-off-by: Birger Koblitz <[email protected]>
Selects the new CEVT timer for Realtek instead of the previous timer driver. While we are at it, we explicitily state we do not use the I2C driver of the RTL9300. Signed-off-by: Birger Koblitz <[email protected]>
This adds the RTL931X sub-target in the realtek target Makefile. Signed-off-by: Birger Koblitz <[email protected]>
Imprves the IRQ request code by using platform_get_irq() which provides better error handling. Signed-off-by: Birger Koblitz <[email protected]>
The RTL839X does not have an internal phy and thus does not need to have any firmware as part of the kernel, especially not firmware for the RTL838X. Signed-off-by: Birger Koblitz <[email protected]>
When a port is brought up, read the SDS-id via the phy_device for a given port and use this to configure the SDS when it is brought up. Signed-off-by: Birger Koblitz <[email protected]>
We were using the PHY-ids (the reg entries in the PHY sections of the .dts) as the port numbers. Now scan the ports section in the .dts, and use the actual port numbers, following the phy-handle to the PHY properties. Signed-off-by: Birger Koblitz <[email protected]>
Adds support for detecting RTL9303 SoCs as found e.g. in the Ubiquiti USW switch. Signed-off-by: Birger Koblitz <[email protected]>
Adds a rtl931x_phylink_mac_config for the RTL931X and improve the handling of the RTL930X phylink configuration. Add separate handling of the RTL839x since some configurations are different from the RTL838X. Signed-off-by: Birger Koblitz <[email protected]>
Adds configuration routines for the internal SerDes of the RTL930X and RTL931X. Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]> fix
Adds the sub-target for the RTL930X-based routers. Adds an initial kernel configuration. Signed-off-by: Birger Koblitz <[email protected]>
We add support for the RTL930X and RTL931X architectures in the gpio-realtek-otto.c driver. Since we do not want to patch the patch, we move the driver itself to drivers/gpio/gpio-realtek-otto.c Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]>
The ZyXEL XGS1250-12 Switch is a 11 + 1 port multi-GBit switch with 8 x 1000BaseT, 3 x 1000/2500/5000/10000BaseT Ethernet ports and 1 SFP+ module slot. Hardware: - RTL9302B SoC - Macronix MX25L12833F (16MB flash) - Nanja NT5CC64M16GP-1 (128MB DDR3 SDRAM) - RTL8231 GPIO extender to control the port LEDs - RTL8218D 8x Gigabit PHY - Aquantia AQR113c 1/2.5/5/10 Gigabit PHYs - SFP+ 10GBit slot Power is supplied via a 12V 2A standard barrel connector. At the right side behind the grid is UART serial connector. A Serial header can be connected to from the outside of the switch trough the airvents with a standard 2.54mm header. Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial connection is via 115200 baud, 8N1. A reset button is accessble through a hole in the front panel Installation: The OpenWRT sysupgrade image can be installed through the OEM web-interface. Signed-off-by: Birger Koblitz <[email protected]>
…ering Use setting functions instead of register numbers in order to clean up the code. Also use enums to define inner/outer VLAN types and the filter type. Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]>
Add the LAG configuration API for DSA as found in Linux 5.12 so that we can implement it in the dsa driver. Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]>
This adds LAG support for all 4 SoC families, including support ofr the use of different distribution algorithm for the load- balancing between individual links. Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]>
Adds the DSA API for bridge configuration (flooding, L2 learning, and aging) offload as found in Linux 5.12 so that we can implement it in our drivver. Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]>
Add functionality to enable or disable L2 learning offload and port flooding for RTL83XX. Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]>
Instead of a generic L2 aging configuration function with complex logic, we implement an individual function for all SoC types. Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]>
In order to receive STP information at the kernel level, we make sure that all Bridge Protocol Data Units are copied to the CPU-Port. Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]>
We need to store and restore MC memberships in HW when a port joins or leaves a bridge as well as when it is enabled or disabled, as these properties should not change in these situations. Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]>
We add HW support routines for the RTL931X SoC family for handling the Packet Inspection Engine, L2 table handling and STP aging. Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]>
We add the RTL931X sub-target with kernel configuration for a dual core MIPS InterAptive CPU. Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]>
For SFP slots on the RTL9302, the link status is not correctly detected. Use the link media status instead. Signed-off-by: Birger Koblitz <[email protected]>
…0/XGS1210 Both the Aquantia AQR113c and the RTL8226 PHYs in the Zyxel XGS1250 and the Zyxel XGS1210 require special polling configuration settings in the RTL930X_SMI_10GPHY_POLLING_REGxx_CFG configuration registers. Set them. Additionally, for RTL 1GBit phys set the RTL930X_SMI_PRVTE_POLLING_CTRL bits in the poll mask. Signed-off-by: Birger Koblitz <[email protected]>
The RTL8221B PHY is a newer version of the RTL8226, also supporting 2.5GBit Ethernet. It is found with RTL931X devices such as the EdgeCore ECS4125-10P Signed-off-by: Sebastian Gottschall <[email protected]> Signed-off-by: Birger Koblitz <[email protected]>
Using the led-set attribute of a port in the dts we allow configuration of the port leds. Each led-set is being defined in the led-set configuration of the .dts, giving a specific configuration to steer the port LEDs via a serial connection. Signed-off-by: Birger Koblitz <[email protected]>
Import commit ("c6af53f038aa3 net: mdio: add helpers to extract clause
45 regad and devad fields") from Linux 5.17 to allow making the MDIO
code in the ethernet driver more readable.
Signed-off-by: Daniel Golle <[email protected]>
* Add missing Clause-45 write support for rtl931x * Switch to use helper functions in all Clause-45 access functions to make the code more readable. * More meaningful/unified debugging output (dynamic kprintf) Signed-off-by: Daniel Golle <[email protected]>
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