Merge pull request chipsalliance#125 from antmicro/akiryk/dec-tl-tests

Microarchitectural test for DEC TL

.github/workflows/test-uarch.yml

@@ -17,6 +17,7 @@ jobs:
           - "block/pic_gw"
           - "block/dma"
           - "block/ifu_compress"
+          - "block/dec_tl"
           - "block/exu_alu"
           - "block/exu_mul"
           - "block/exu_div"

verification/block/dec_tl/Makefile

@@ -0,0 +1,17 @@
+null  :=
+space := $(null) #
+comma := ,
+
+CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+SRCDIR := $(abspath $(CURDIR)../../../../design)
+
+TEST_FILES   = $(sort $(wildcard test_*.py))
+
+MODULE      ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
+TOPLEVEL     = el2_dec_trigger_wrapper
+
+VERILOG_SOURCES  = \
+    $(CURDIR)/dec_tl/el2_dec_trigger_wrapper.sv \
+    $(SRCDIR)/dec/el2_dec_trigger.sv
+
+include $(CURDIR)/../common.mk

verification/block/dec_tl/el2_dec_trigger_wrapper.sv

@@ -0,0 +1,41 @@
+// Copyright (c) 2023 Antmicro
+// SPDX-License-Identifier: Apache-2.0
+module el2_dec_trigger_wrapper
+  import el2_pkg::*;
+#(
+    `include "el2_param.vh"
+) (
+    input logic [31:1] dec_i0_pc_d,
+
+    // Unpacked [3:0] trigger_pkt_t
+    input logic [3:0] select,
+    input logic [3:0] match,
+    input logic [3:0] store,
+    input logic [3:0] load,
+    input logic [3:0] execute,
+    input logic [3:0] m,
+
+    input logic [31:0] tdata[4],
+
+    output logic [3:0] dec_i0_trigger_match_d
+);
+
+  // Pack triggers
+  el2_trigger_pkt_t [3:0] trigger_pkt_any;
+  for (genvar i = 0; i < 4; i++) begin : g_trigger_assigns
+    assign trigger_pkt_any[i].select  = select[i];
+    assign trigger_pkt_any[i].match   = match[i];
+    assign trigger_pkt_any[i].store   = store[i];
+    assign trigger_pkt_any[i].load    = load[i];
+    assign trigger_pkt_any[i].execute = execute[i];
+    assign trigger_pkt_any[i].m       = m[i];
+    assign trigger_pkt_any[i].tdata2  = tdata[i];
+  end
+
+  // The trigger unit
+  el2_dec_trigger tu (
+      .dec_i0_pc_d(dec_i0_pc_d[31:1]),
+      .*
+  );
+
+endmodule

verification/block/dec_tl/test_dec_tl.py

@@ -0,0 +1,28 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+import random
+
+import pyuvm
+from cocotb.triggers import ClockCycles
+from pyuvm import *
+from testbench import TlSequence, BaseTest
+
+# =============================================================================
+
+
+@pyuvm.test()
+class TestTriggerLogic(BaseTest):
+    def end_of_elaboration_phase(self):
+        super().end_of_elaboration_phase()
+        self.seq = TlSequence("stimulus")
+
+    async def run_phase(self):
+        self.raise_objection()
+
+        # Run the actual test
+        await self.run()
+
+        self.drop_objection()
+
+    async def run(self):
+        await self.seq.start(self.env.tl_seqr)