Merge pull request chipsalliance#123 from antmicro/dccm_test

Microarchitectural test for DCCM

.github/workflows/test-uarch.yml

@@ -21,6 +21,7 @@ jobs:
           - "block/exu_mul"
           - "block/exu_div"
           - "block/iccm"
+          - "block/dccm"
     env:
       CCACHE_DIR: "/opt/verification/.cache/"
       VERILATOR_VERSION: v5.010

verification/block/dccm/Makefile

@@ -0,0 +1,23 @@
+
+null  :=
+space := $(null) #
+comma := ,
+
+CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+SRCDIR := $(abspath $(CURDIR)../../../../design)
+
+TEST_FILES   = $(sort $(wildcard test_*.py))
+
+MODULE      ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
+TOPLEVEL     = el2_lsu_dccm_mem_wrapper
+
+VERILOG_SOURCES  = \
+    $(CURDIR)/dccm/el2_lsu_dccm_mem_wrapper.sv \
+    $(SRCDIR)/lsu/el2_lsu_dccm_mem.sv \
+    $(SRCDIR)/lib/mem_lib.sv
+
+# Undefine the VERILATOR macro to make the code use actual RAM cells instead
+# of simulation models
+EXTRA_ARGS += -UVERILATOR
+
+include $(CURDIR)/../common.mk

verification/block/dccm/el2_lsu_dccm_mem_wrapper.sv

@@ -0,0 +1,55 @@
+module el2_lsu_dccm_mem_wrapper
+  import el2_pkg::*;
+#(
+    `include "el2_param.vh"
+)
+(
+    input logic clk,
+    input logic active_clk,
+    input logic rst_l,
+    input logic clk_override,
+
+    input logic dccm_wren,
+    input logic dccm_rden,
+    input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo,
+    input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi,
+    input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo,
+    input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi,
+    input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
+    input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
+
+    // el2_dccm_ext_in_pkt_t
+    input logic dccm_ext_in_pkt_TEST1,
+    input logic dccm_ext_in_pkt_RME,
+    input logic [3:0] dccm_ext_in_pkt_RM,
+    input logic dccm_ext_in_pkt_LS,
+    input logic dccm_ext_in_pkt_DS,
+    input logic dccm_ext_in_pkt_SD,
+    input logic dccm_ext_in_pkt_TEST_RNM,
+    input logic dccm_ext_in_pkt_BC1,
+    input logic dccm_ext_in_pkt_BC2,
+
+    output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
+    output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
+
+    input logic scan_mode
+);
+
+  // Pack dccm_ext_in_pkt
+  el2_dccm_ext_in_pkt_t [pt.DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt;
+
+  for (genvar i = 0; i < pt.DCCM_NUM_BANKS; i++) begin
+      assign dccm_ext_in_pkt[i].TEST1    = dccm_ext_in_pkt_TEST1;
+      assign dccm_ext_in_pkt[i].RME      = dccm_ext_in_pkt_RME;
+      assign dccm_ext_in_pkt[i].RM       = dccm_ext_in_pkt_RM;
+      assign dccm_ext_in_pkt[i].LS       = dccm_ext_in_pkt_LS;
+      assign dccm_ext_in_pkt[i].DS       = dccm_ext_in_pkt_DS;
+      assign dccm_ext_in_pkt[i].SD       = dccm_ext_in_pkt_SD;
+      assign dccm_ext_in_pkt[i].TEST_RNM = dccm_ext_in_pkt_TEST_RNM;
+      assign dccm_ext_in_pkt[i].BC1      = dccm_ext_in_pkt_BC1;
+      assign dccm_ext_in_pkt[i].BC2      = dccm_ext_in_pkt_BC2;
+  end
+
+  el2_lsu_dccm_mem mem (.*);
+
+endmodule

verification/block/dccm/test_readwrite.py

@@ -0,0 +1,61 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+import random
+
+import pyuvm
+from cocotb.triggers import ClockCycles
+from pyuvm import *
+from testbench import BaseTest, MemReadItem, MemWriteItem
+
+# =============================================================================
+
+
+class ReadWriteSequence(uvm_sequence):
+    """
+    A sequencer that issues a random sequence of writes followed by a
+    randomized sequence of reads containing the same addresses previously
+    written to.
+    """
+
+    def __init__(self, name):
+        super().__init__(name)
+
+    async def body(self):
+        count = ConfigDB().get(None, "", "TEST_ITERATIONS")
+        burst = ConfigDB().get(None, "", "TEST_BURST_LEN")
+
+        awidth = ConfigDB().get(None, "", "DCCM_BITS")
+        dwidth = ConfigDB().get(None, "", "DCCM_FDATA_WIDTH")
+
+        for i in range(count):
+
+            # Randomize unique addresses (aligned)
+            addrs = set([
+                random.randrange(0, 1 << awidth) & 0xFFFFFFFC
+                for i in range(burst)
+            ])
+
+            # Issue writes, randomize data
+            for addr in addrs:
+                data = random.randrange(0, 1 << dwidth)
+
+                item = MemWriteItem(addr, data)
+                await self.start_item(item)
+                await self.finish_item(item)
+
+            # Issue random reads for written addresses
+            random.shuffle(list(set(addrs)))
+            for addr in addrs:
+                item = MemReadItem(addr, data)
+                await self.start_item(item)
+                await self.finish_item(item)
+
+
+@pyuvm.test()
+class TestReadWrite(BaseTest):
+    def end_of_elaboration_phase(self):
+        super().end_of_elaboration_phase()
+        self.seq = ReadWriteSequence("stimulus")
+
+    async def run(self):
+        await self.seq.start(self.env.mem_seqr)