Merge pull request chipsalliance#124 from antmicro/iccm_test

Microarchitectural test for ICCM

.github/workflows/test-uarch.yml

@@ -20,6 +20,7 @@ jobs:
           - "block/exu_alu"
           - "block/exu_mul"
           - "block/exu_div"
+          - "block/iccm"
     env:
       CCACHE_DIR: "/opt/verification/.cache/"
       VERILATOR_VERSION: v5.010

verification/block/iccm/Makefile

@@ -0,0 +1,23 @@
+
+null  :=
+space := $(null) #
+comma := ,
+
+CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+SRCDIR := $(abspath $(CURDIR)../../../../design)
+
+TEST_FILES   = $(sort $(wildcard test_*.py))
+
+MODULE      ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
+TOPLEVEL     = el2_ifu_iccm_mem_wrapper
+
+VERILOG_SOURCES  = \
+    $(CURDIR)/iccm/el2_ifu_iccm_mem_wrapper.sv \
+    $(SRCDIR)/ifu/el2_ifu_iccm_mem.sv \
+    $(SRCDIR)/lib/mem_lib.sv
+
+# Undefine the VERILATOR macro to make the code use actual RAM cells instead
+# of simulation models
+EXTRA_ARGS += -UVERILATOR
+
+include $(CURDIR)/../common.mk

verification/block/iccm/el2_ifu_iccm_mem_wrapper.sv

@@ -0,0 +1,56 @@
+// Copyright (c) 2023 Antmicro
+// SPDX-License-Identifier: Apache-2.0
+
+module el2_ifu_iccm_mem_wrapper
+    import el2_pkg::*;
+#(
+    `include "el2_param.vh"
+)(
+    input logic clk,
+    input logic active_clk,
+    input logic rst_l,
+    input logic clk_override,
+
+    input logic iccm_wren,
+    input logic iccm_rden,
+    input logic [pt.ICCM_BITS-1:1] iccm_rw_addr,
+    input logic iccm_buf_correct_ecc,
+    input logic iccm_correction_state,
+    input logic [2:0] iccm_wr_size,
+    input logic [77:0] iccm_wr_data,
+
+    // Unwrapped iccm_ext_in_pkt
+    input logic iccm_ext_in_pkt_TEST1,
+    input logic iccm_ext_in_pkt_RME,
+    input logic [3:0] iccm_ext_in_pkt_RM,
+    input logic iccm_ext_in_pkt_LS,
+    input logic iccm_ext_in_pkt_DS,
+    input logic iccm_ext_in_pkt_SD,
+    input logic iccm_ext_in_pkt_TEST_RNM,
+    input logic iccm_ext_in_pkt_BC1,
+    input logic iccm_ext_in_pkt_BC2,
+
+    output logic [63:0] iccm_rd_data,
+    output logic [77:0] iccm_rd_data_ecc,
+    input logic scan_mode
+);
+
+    // Pack iccm_ext_in_pkt
+    el2_ccm_ext_in_pkt_t [pt.ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt;
+
+    for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin
+        assign iccm_ext_in_pkt[i].TEST1 = iccm_ext_in_pkt_TEST1;
+        assign iccm_ext_in_pkt[i].RME = iccm_ext_in_pkt_RME;
+        assign iccm_ext_in_pkt[i].RM = iccm_ext_in_pkt_RM;
+        assign iccm_ext_in_pkt[i].LS = iccm_ext_in_pkt_LS;
+        assign iccm_ext_in_pkt[i].DS = iccm_ext_in_pkt_DS;
+        assign iccm_ext_in_pkt[i].SD = iccm_ext_in_pkt_SD;
+        assign iccm_ext_in_pkt[i].TEST_RNM = iccm_ext_in_pkt_TEST_RNM;
+        assign iccm_ext_in_pkt[i].BC1 = iccm_ext_in_pkt_BC1;
+        assign iccm_ext_in_pkt[i].BC2 = iccm_ext_in_pkt_BC2;
+    end
+
+    // The ICCM module
+    el2_ifu_iccm_mem mem (.*);
+
+endmodule

verification/block/iccm/test_readwrite.py

@@ -0,0 +1,59 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+import random
+
+import pyuvm
+from pyuvm import *
+from testbench import BaseTest, MemReadItem, MemWriteItem
+
+# =============================================================================
+
+
+class ReadWriteSequence(uvm_sequence):
+    """
+    A sequencer that issues a random sequence of writes followed by a
+    randomized sequence of reads containing the same addresses previously
+    written to.
+    """
+
+    def __init__(self, name):
+        super().__init__(name)
+
+    async def body(self):
+        count = ConfigDB().get(None, "", "TEST_ITERATIONS")
+        burst = ConfigDB().get(None, "", "TEST_BURST_LEN")
+
+        awidth = (
+            ConfigDB().get(None, "", "ICCM_BITS") - 1
+        )  # Address input declared as [pt.ICCM_BITS-1:1]
+        dwidth = 64  # Fixed
+
+        for i in range(count):
+            # Randomize unique addresses (aligned to 8)
+            addrs = set([random.randrange(0, 1 << awidth) & ~7 for i in range(burst)])
+
+            # Issue writes, randomize data
+            for addr in addrs:
+                data = random.randrange(0, 1 << dwidth)
+
+                item = MemWriteItem(addr, data)
+                await self.start_item(item)
+                await self.finish_item(item)
+
+            # Issue random reads for written addresses
+            addrs = list(set(addrs))
+            random.shuffle(addrs)
+            for addr in addrs:
+                item = MemReadItem(addr, data)
+                await self.start_item(item)
+                await self.finish_item(item)
+
+
+@pyuvm.test()
+class TestReadWrite(BaseTest):
+    def end_of_elaboration_phase(self):
+        super().end_of_elaboration_phase()
+        self.seq = ReadWriteSequence("stimulus")
+
+    async def run(self):
+        await self.seq.start(self.env.mem_seqr)