Verific frontend: fix top_bound/bottom_bound attributes

[nakengelhardt]

What are the reasons/motivation for this change?

Fixes two issues:

1. Erroneous top_bound/bottom_bound attributes appear on SystemVerilog wires
2. top_bound/bottom_bound attributes are the wrong size on VHDL null ranges, and the value of the bounds may be truncated. It's not possible to tell the size of the wire from the type_range object in these cases.

Explain how this is achieved.

1. Only run on nets coming from VHDL
2. Pass in an optional width hint that import_attributes can use to determine the size of the bounds.

If applicable, please suggest to reviewers how they can test the change.

Expanded tests for many port types are included.

[mmicko]

LGTM