Improve opt_expr performance

[povik]

See the commits. This avoids having to populate dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;, and it saves repeated conversions of type IDs to strings (36 times per cell for one iteration of the loop in opt_expr). Allocating a string for the IDs was significant enough to stand out when watching where opt_expr spends its time.

[widlarizer]

With -noopt hacked into proc as called by techmap in the first part of the failing test, before opt_expr would be called check can be called instead and it does reveal a logic loop

[widlarizer]

Since

yosys/techlibs/xilinx/cells_sim.v

Line 3900 in 1e401c3

P = Pd;

and

yosys/techlibs/xilinx/cells_sim.v

Line 3726 in 1e401c3

Z = P;

and Pd is constructed from expressions that combinationally depend on Z, a comb loop is apparently generated. However, it is unreachable, since one of the two statements I linked depends on different values of the parameter PREG. The inactive statements only get resolved by opt, which is what the failing test actually tests for

[widlarizer]

I think if you're okay with it we should just supress the warning with -expect. See commit de79978 for how we got to the current version of techlibs/xilinx/cells_sim.v

[povik]

Ah so it was the new warning which was tripping up the tests. I am fine with suppressing it to pass the test, but I think we should discuss whether we want the warning in the first place.

In the meantime we have changed check to allow coarse loops, and those would trigger the warning too. So we need to account for that in the wording.