Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_w…

…idth opt_demorgan: skip zero width cells
YosysHQ · Nov 20, 2024 · cc17d5b · cc17d5b
2 parents 18459b4 + e105cae
commit cc17d5b
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diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc
@@ -39,6 +39,10 @@ void demorgan_worker(
 		return;
 
 	auto insig = sigmap(cell->getPort(ID::A));
+
+	if (GetSize(insig) < 1)
+		return;
+
 	log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
 	int num_inverted = 0;
 	for(int i=0; i<GetSize(insig); i++)

diff --git a/tests/opt/bug4610.ys b/tests/opt/bug4610.ys
@@ -0,0 +1,15 @@
+read_ilang <<EOT
+autoidx 1
+module \top
+  wire output 1 \Y
+  cell $reduce_or $reduce_or$rtl.v:29$20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 0
+    parameter \Y_WIDTH 1
+    connect \A { }
+    connect \Y \Y
+  end
+end
+EOT
+
+equiv_opt -assert opt_demorgan