Test all files in verilog dir

tests/functional/.gitignore

@@ -1,5 +1,5 @@
-and_cxxrtl.cc
-and_functional_cxx.cc
+my_module_cxxrtl.cc
+my_module_functional_cxx.cc
 vcd_harness
 cxxrtl.vcd
 functional_cxx.vcd

tests/functional/run-test.sh

@@ -2,19 +2,29 @@
 
 set -ex
 
-../../yosys -p "read_verilog verilog/and.v; write_cxxrtl and_cxxrtl.cc; write_functional_cxx and_functional_cxx.cc"
-${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness
-# Generate VCD files cxxrtl.vcd and functional_cxx.vcd
-./vcd_harness
-# Run vcdiff and capture the output
-output=$(vcdiff cxxrtl.vcd functional_cxx.vcd)
+# Loop through all Verilog files in the verilog directory
+for verilog_file in verilog/*.v; do
+    # Run yosys to process each Verilog file
+    ../../yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc"
 
-# Check if there is any output
-if [ -n "$output" ]; then
-    echo "Differences detected:"
-    echo "$output"
-    exit 1
-else
-    echo "No differences detected."
-    exit 0
-fi
+    # Compile the generated C++ files with vcd_harness.cpp
+    ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ../../backends/functional/cxx_runtime/ -I ../../backends/cxxrtl/runtime/ -o vcd_harness
+
+    # Generate VCD files cxxrtl.vcd and functional_cxx.vcd
+    ./vcd_harness
+
+    # Run vcdiff and capture the output
+    output=$(vcdiff cxxrtl.vcd functional_cxx.vcd)
+
+    # Check if there is any output
+    if [ -n "$output" ]; then
+        echo "Differences detected in $verilog_file:"
+        echo "$output"
+        exit 1
+    else
+        echo "No differences detected in $verilog_file."
+    fi
+done
+
+# If all files are processed without differences
+exit 0

tests/functional/vcd_harness.cpp

@@ -5,8 +5,8 @@
 
 #include <cxxrtl/cxxrtl_vcd.h>
 
-#include "and_cxxrtl.cc"
-#include "and_functional_cxx.cc"
+#include "my_module_cxxrtl.cc"
+#include "my_module_functional_cxx.cc"
 
 struct DumpHeader {
     std::ofstream &ofs;

tests/functional/verilog/add.v

@@ -0,0 +1,9 @@
+module my_module(
+		 input	a,
+		 input	b,
+		 output	sum
+		 );
+   // Perform addition
+   assign sum = a + b;
+
+endmodule

tests/functional/verilog/and.v

@@ -1,9 +1,9 @@
 module my_module(
-		 input	a,
-		 input	b,
-		 output	sum
-		 );
-   // Perform addition
-   assign sum = a + b;
+    input a,
+    input b,
+    output y
+);
+   // Perform AND
+   assign y = a & b;
 
 endmodule

tests/functional/verilog/my_module_div.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a / b;
+
+endmodule

tests/functional/verilog/my_module_eqx.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a === b;
+
+endmodule

tests/functional/verilog/my_module_ge.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a >= b;
+
+endmodule

tests/functional/verilog/my_module_gt.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a > b;
+
+endmodule

tests/functional/verilog/my_module_le.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a <= b;
+
+endmodule

tests/functional/verilog/my_module_logic_and.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a && b;
+
+endmodule

tests/functional/verilog/my_module_logic_or.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a || b;
+
+endmodule

tests/functional/verilog/my_module_lt.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a < b;
+
+endmodule

tests/functional/verilog/my_module_mod.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a % b;
+
+endmodule

tests/functional/verilog/my_module_mul.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a * b;
+
+endmodule

tests/functional/verilog/my_module_ne.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a != b;
+
+endmodule

tests/functional/verilog/my_module_nex.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a !== b;
+
+endmodule

tests/functional/verilog/my_module_or.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a | b;
+
+endmodule

tests/functional/verilog/my_module_pow.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a ** b;
+
+endmodule

tests/functional/verilog/my_module_shl.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a << b;
+
+endmodule

tests/functional/verilog/my_module_shr.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a >> b;
+
+endmodule

tests/functional/verilog/my_module_sshl.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a <<< b;
+
+endmodule

tests/functional/verilog/my_module_sshr.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a >>> b;
+
+endmodule

tests/functional/verilog/my_module_sub.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a - b;
+
+endmodule

tests/functional/verilog/my_module_xnor.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a ~^ b;
+
+endmodule

tests/functional/verilog/my_module_xor.v

@@ -0,0 +1,9 @@
+module my_module(
+    input a,
+    input b,
+    output y
+);
+   // Perform operation
+   assign y = a ^ b;
+
+endmodule