Fix sim model

YosysHQ · May 28, 2024 · 66ddcc7 · 66ddcc7
1 parent a33ad50
commit 66ddcc7
Showing 1 changed file with 48 additions and 48 deletions.
diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
@@ -241,30 +241,30 @@ module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4,
     input AI7;
     input AI8;
     input AI9;
-    output AO1;
-    output AO10;
-    output AO11;
-    output AO12;
-    output AO13;
-    output AO14;
-    output AO15;
-    output AO16;
-    output AO17;
-    output AO18;
-    output AO19;
-    output AO2;
-    output AO20;
-    output AO21;
-    output AO22;
-    output AO23;
-    output AO24;
-    output AO3;
-    output AO4;
-    output AO5;
-    output AO6;
-    output AO7;
-    output AO8;
-    output AO9;
+    output reg AO1;
+    output reg AO10;
+    output reg AO11;
+    output reg AO12;
+    output reg AO13;
+    output reg AO14;
+    output reg AO15;
+    output reg AO16;
+    output reg AO17;
+    output reg AO18;
+    output reg AO19;
+    output reg AO2;
+    output reg AO20;
+    output reg AO21;
+    output reg AO22;
+    output reg AO23;
+    output reg AO24;
+    output reg AO3;
+    output reg AO4;
+    output reg AO5;
+    output reg AO6;
+    output reg AO7;
+    output reg AO8;
+    output reg AO9;
     input AR;
     input AWE;
     input BA1;
@@ -314,30 +314,30 @@ module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4,
     input BI7;
     input BI8;
     input BI9;
-    output BO1;
-    output BO10;
-    output BO11;
-    output BO12;
-    output BO13;
-    output BO14;
-    output BO15;
-    output BO16;
-    output BO17;
-    output BO18;
-    output BO19;
-    output BO2;
-    output BO20;
-    output BO21;
-    output BO22;
-    output BO23;
-    output BO24;
-    output BO3;
-    output BO4;
-    output BO5;
-    output BO6;
-    output BO7;
-    output BO8;
-    output BO9;
+    output reg BO1;
+    output reg BO10;
+    output reg BO11;
+    output reg BO12;
+    output reg BO13;
+    output reg BO14;
+    output reg BO15;
+    output reg BO16;
+    output reg BO17;
+    output reg BO18;
+    output reg BO19;
+    output reg BO2;
+    output reg BO20;
+    output reg BO21;
+    output reg BO22;
+    output reg BO23;
+    output reg BO24;
+    output reg BO3;
+    output reg BO4;
+    output reg BO5;
+    output reg BO6;
+    output reg BO7;
+    output reg BO8;
+    output reg BO9;
     input BR;
     input BWE;
     parameter mcka_edge = 1'b0;