fix proc, reduce warnings

passes/cmds/glift.cc

@@ -343,7 +343,7 @@ struct GliftWorker {
 				//recurse to GLIFT model the child module. However, we need to augment the ports list
 				//with taint signals and connect the new ports to the corresponding taint signals.
 				RTLIL::Module *cell_module_def = module->design->module(cell->type);
-				auto orig_ports = cell->connections();
+				auto orig_ports = cell->connections().as_dict();
 				log("Adding cell %s\n", cell_module_def->name.c_str());
 				for (auto &&it : orig_ports) {
 					RTLIL::SigSpec port = it.second;

passes/proc/proc_mux.cc

@@ -252,7 +252,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 	return RTLIL::SigSpec(result_wire);
 }
 
-void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
+void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
 {
 	log_assert(last_mux_cell != NULL);
 	log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size());

passes/tests/test_cell.cc

@@ -344,7 +344,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 
 	if (constmode)
 	{
-		auto conn_list = cell->connections();
+		auto conn_list = cell->connections().as_dict();
 		for (auto conn : conn_list)
 		{
 			RTLIL::SigSpec sig = conn.second;