[AIE2] Enable HL by default

Xilinx · Aug 1, 2024 · fab10ba · fab10ba
1 parent 8febe27
commit fab10ba
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Showing 7 changed files with 16 additions and 17 deletions.
diff --git a/llvm/lib/Target/AIE/AIE2TargetTransformInfo.cpp b/llvm/lib/Target/AIE/AIE2TargetTransformInfo.cpp
@@ -21,12 +21,12 @@ using namespace llvm;
 static cl::opt<bool>
     EnableAIEHardwareLoops("enable-aie-hardware-loops",
                            cl::desc("Enable hardware loops on AIE"),
-                           cl::init(false), cl::Hidden);
+                           cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
     AllowAIEZOL("enable-aie-zero-overhead-loops",
                 cl::desc("Enable true zero overhead hardware loops on AIE"),
-                cl::init(false), cl::Hidden);
+                cl::init(true), cl::Hidden);
 
 static cl::opt<int> MinIterCountHLReject(
     "aie-hardware-loops-minitercount", cl::Hidden, cl::init(3),

diff --git a/llvm/test/CodeGen/AIE/aie2/end-to-end/Conv2D-red-swp.ll b/llvm/test/CodeGen/AIE/aie2/end-to-end/Conv2D-red-swp.ll
@@ -5,9 +5,9 @@
 ; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 ;
 ; (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
-; RUN: llc -O2 -mtriple=aie2 --enable-pipeliner=1 %s -o - | FileCheck %s --check-prefix=DCL
-; RUN: llc -O2 -mtriple=aie2 --enable-pipeliner=1 --enable-aie-hardware-loops=true \
-; RUN:    --enable-aie-zero-overhead-loops=true %s -o - | FileCheck %s --check-prefix=ZOL
+; RUN: llc -O2 -mtriple=aie2 --enable-pipeliner=1 --enable-aie-hardware-loops=false \
+; RUN:     --enable-aie-zero-overhead-loops=false %s -o - | FileCheck %s --check-prefix=DCL
+; RUN: llc -O2 -mtriple=aie2 --enable-pipeliner=1 %s -o - | FileCheck %s --check-prefix=ZOL
 ; RUN: llc -O2 -mtriple=aie2 --enable-pipeliner=0 %s -o - --debug-only=machine-scheduler  \
 ; RUN:    2>&1 | %imisched -d - \
 ; RUN:    | FileCheck %s --check-prefix=SCHED-DUMP

diff --git a/llvm/test/CodeGen/AIE/aie2/hardware-loops/nested.ll b/llvm/test/CodeGen/AIE/aie2/hardware-loops/nested.ll
@@ -5,7 +5,7 @@
 ; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 ;
 ; (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
-; RUN: llc -O2 -mtriple=aie2 --issue-limit=1 --enable-aie-hardware-loops \
+; RUN: llc -O2 -mtriple=aie2 --issue-limit=1 --enable-aie-zero-overhead-loops=false \
 ; RUN:    --aie-force-hl-gen=true %s -o - | FileCheck %s
 
 ; Check that we recognize the two level nested loops as hardware loop candidates.

diff --git a/llvm/test/CodeGen/AIE/aie2/hardware-loops/sibling.ll b/llvm/test/CodeGen/AIE/aie2/hardware-loops/sibling.ll
@@ -5,7 +5,7 @@
 ; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 ;
 ; (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
-; RUN: llc -O2 -mtriple=aie2 --issue-limit=1 --enable-aie-hardware-loops \
+; RUN: llc -O2 -mtriple=aie2 --issue-limit=1 --enable-aie-zero-overhead-loops=false \
 ; RUN:    --aie-force-hl-gen=true %s -o - | FileCheck %s
 
 define void @sibling(ptr nocapture %out, ptr nocapture readonly %in, i32 noundef %size, i32 noundef %size2) {

diff --git a/llvm/test/CodeGen/AIE/aie2/hardware-loops/simple.ll b/llvm/test/CodeGen/AIE/aie2/hardware-loops/simple.ll
@@ -5,7 +5,7 @@
 ; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 ;
 ; (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
-; RUN: llc -O2 -mtriple=aie2 --issue-limit=1 --enable-aie-hardware-loops \
+; RUN: llc -O2 -mtriple=aie2 --issue-limit=1 --enable-aie-zero-overhead-loops=false \
 ; RUN:    --aie-force-hl-gen=true %s -o - | FileCheck %s
 
 define void @simple(ptr nocapture %out, ptr nocapture readonly %in, i32 noundef %size) {

diff --git a/llvm/test/Transforms/HardwareLoops/AIE/profitable.ll b/llvm/test/Transforms/HardwareLoops/AIE/profitable.ll
@@ -5,10 +5,10 @@
 ; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 ;
 ; (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
-; RUN: opt -mtriple=aie2 --passes="hardware-loops" --enable-aie-hardware-loops --aie-force-hl-gen \
-; RUN:     %s -S -o - | FileCheck %s
-; RUN: opt -mtriple=aie2 --passes="hardware-loops" --enable-aie-hardware-loops \
-; RUN:     --enable-aie-zero-overhead-loops --aie-force-hl-gen %s -S -o - | \
+; RUN: opt -mtriple=aie2 --passes="hardware-loops" --aie-force-hl-gen \
+; RUN:     --enable-aie-zero-overhead-loops=false %s -S -o - | FileCheck %s
+; RUN: opt -mtriple=aie2 --passes="hardware-loops" \
+; RUN:     --aie-force-hl-gen %s -S -o - | \
 ; RUN:     FileCheck %s --check-prefix=CHECK-ZOL
 
 ; We can support nested hardware loops.

diff --git a/llvm/test/Transforms/HardwareLoops/AIE/unprofitable.ll b/llvm/test/Transforms/HardwareLoops/AIE/unprofitable.ll
@@ -4,13 +4,12 @@
 ; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 ;
 ; (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
-; RUN: opt -mtriple=aie2 --passes="hardware-loops" --enable-aie-hardware-loops \
+; RUN: opt -mtriple=aie2 --passes="hardware-loops" --enable-aie-zero-overhead-loops=false \
 ; RUN:     --aie-force-hl-gen %s -S -o - | FileCheck %s
-; RUN: opt -mtriple=aie2 --passes="hardware-loops" --enable-aie-hardware-loops \
-; RUN:     --enable-aie-zero-overhead-loops --aie-force-hl-gen %s -S -o - | \
+; RUN: opt -mtriple=aie2 --passes="hardware-loops" --aie-force-hl-gen %s -S -o - | \
 ; RUN:     FileCheck --check-prefix=CHECK-ZOL %s
-; RUN: opt -mtriple=aie2 --passes="hardware-loops" --enable-aie-hardware-loops \
-; RUN:     -pass-remarks-analysis=hardware-loops --aie-force-hl-gen  %s -S -o - 2>&1 | \
+; RUN: opt -mtriple=aie2 --passes="hardware-loops" -pass-remarks-analysis=hardware-loops \
+; RUN:      --aie-force-hl-gen  %s -S -o - 2>&1 | \
 ; RUN:     FileCheck %s --check-prefix=CHECK-REMARKS