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Pull requests: Xilinx/llvm-aie
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[AIE2P] Instruction select G_TRUNC for vector operands
#341
opened Feb 6, 2025 by
niwinanto
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[AIE2P] Improve
RegbankSelect
handling for load/store offset and post-increment addressing modes
#337
opened Feb 6, 2025 by
abnikant
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[AIE2P] Fix align requirement for wide vector load/store and split 32 aligned load/store instead of scalarizing them
#321
opened Jan 30, 2025 by
khallouh
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Improvements in resource conflict detection related to slots
#305
opened Jan 23, 2025 by
martien-de-jong
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Draft
Reclaim size regression for aligning fallthrough-only blocks
#303
opened Jan 23, 2025 by
abhinay-anubola
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Draft
[AIE] Solve it. Work In Progress adding a solver-based postpipeliner
#255
opened Jan 10, 2025 by
martien-de-jong
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Draft
[AIE NFC] Postpipeliner cleanups and refactorings
#253
opened Jan 8, 2025 by
martien-de-jong
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[AIEX] Schedule SWP epilogue with "free" instructions
#247
opened Dec 10, 2024 by
andcarminati
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Add support for bfloat in VInsert PreLegalizerCombiner
#243
opened Nov 21, 2024 by
abhinay-anubola
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Support for allowing direct VEXTRACT to 20-bit registers
#233
opened Nov 8, 2024 by
abhinay-anubola
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[AIEX] Ignore bank conflict if in the next cycle we cannot schedule the instruction.
#229
opened Nov 1, 2024 by
krishnamtibrewala
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Draft
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Updated in the last three days: updated:>2025-02-09.