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[AIE2p] Enable register re-allocation
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@gbossu
gbossu committed Feb 13, 2025
1 parent 256eb91 commit 3e75a3d
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Showing 6 changed files with 89 additions and 20 deletions.
5 changes: 1 addition & 4 deletions llvm/lib/Target/AIE/AIE2TargetMachine.cpp
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Expand Up @@ -27,10 +27,6 @@ cl::opt<bool>
EnableSubregRenaming("aie-subreg-renaming", cl::Hidden, cl::init(false),
cl::desc("Enable RenameIndependentSubregs pass"));

static cl::opt<bool>
EnableWAWRegRewrite("aie-wawreg-rewrite",
cl::desc("Enable the WAW Register Renaming in loops"),
cl::init(true), cl::Hidden);
static cl::opt<bool>
EnableReservedRegsLICM("aie-reserved-regs-licm", cl::Hidden, cl::init(true),
cl::desc("Enable LICM for some reserved registers"));
Expand All @@ -45,6 +41,7 @@ extern cl::opt<bool> EnableStagedRA;
extern cl::opt<bool> EnableSuperRegSplitting;
extern cl::opt<bool> AllocateMRegsFirst;
extern cl::opt<bool> EnablePreMISchedCoalescer;
extern cl::opt<bool> EnableWAWRegRewrite;

extern bool AIEDumpArtifacts;

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5 changes: 5 additions & 0 deletions llvm/lib/Target/AIE/AIEBaseTargetMachine.cpp
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Expand Up @@ -77,6 +77,11 @@ cl::opt<bool>
EnableStagedRA("aie-staged-ra", cl::Hidden, cl::init(true),
cl::desc("Enable multi-stage register allocation"));

cl::opt<bool>
EnableWAWRegRewrite("aie-wawreg-rewrite",
cl::desc("Enable the WAW Register Renaming in loops"),
cl::init(true), cl::Hidden);

cl::opt<bool>
EnableSuperRegSplitting("aie-split-superregs", cl::Hidden, cl::init(true),
cl::desc("Enable splitting super-regs into their "
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5 changes: 5 additions & 0 deletions llvm/lib/Target/AIE/aie2p/AIE2PTargetMachine.cpp
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Expand Up @@ -22,6 +22,7 @@ extern cl::opt<bool> EnableSuperRegSplitting;
extern cl::opt<bool> AllocateMRegsFirst;
extern cl::opt<bool> EnablePreMISchedCoalescer;
extern cl::opt<bool> EnableAddressChaining;
extern cl::opt<bool> EnableWAWRegRewrite;

void AIE2PTargetMachine::anchor() {}

Expand Down Expand Up @@ -102,6 +103,10 @@ bool AIE2PPassConfig::addRegAssignAndRewriteOptimized() {
addPass(createAIESuperRegRewriter());
}
addPass(createGreedyRegisterAllocator());
if (EnableWAWRegRewrite) {
addPass(createAIEWawRegRewriter());
addPass(createGreedyRegisterAllocator());
}
addPass(createVirtRegRewriter());

return true;
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4 changes: 4 additions & 0 deletions llvm/test/CodeGen/AIE/aie2p/llc-pipeline-aie2p.ll
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Expand Up @@ -235,6 +235,8 @@
; AIE-O1-NEXT: Greedy Register Allocator
; AIE-O1-NEXT: AIE super-reg rewrite
; AIE-O1-NEXT: Greedy Register Allocator
; AIE-O1-NEXT: AIE waw-reg rewrite
; AIE-O1-NEXT: Greedy Register Allocator
; AIE-O1-NEXT: Virtual Register Rewriter
; AIE-O1-NEXT: Stack Slot Coloring
; AIE-O1-NEXT: AIE 1D operands to 2D/3D rewriter
Expand Down Expand Up @@ -441,6 +443,8 @@
; AIE-O23-NEXT: Greedy Register Allocator
; AIE-O23-NEXT: AIE super-reg rewrite
; AIE-O23-NEXT: Greedy Register Allocator
; AIE-O23-NEXT: AIE waw-reg rewrite
; AIE-O23-NEXT: Greedy Register Allocator
; AIE-O23-NEXT: Virtual Register Rewriter
; AIE-O23-NEXT: Stack Slot Coloring
; AIE-O23-NEXT: AIE 1D operands to 2D/3D rewriter
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56 changes: 56 additions & 0 deletions llvm/test/CodeGen/AIE/aie2p/ra/waw_reg_renaming.mir
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@@ -0,0 +1,56 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# NOTE: Example file for Write After Write Register Renaming in Loop test
#
# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
# See https://llvm.org/LICENSE.txt for license information.
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
#
# (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates

# Basic test for the WAW register renaming pass. Check AIE2 tests for more coverage.

# RUN: llc -mtriple=aie2p -verify-machineinstrs --start-before=greedy --stop-after=virtregrewriter %s -o - | FileCheck %s

# Make sure VLD and VMAX define different X registers.
---
name: simple_waw_replacement
alignment: 16
legalized: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: simple_waw_replacement
; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $p0, $p1, $r0, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: LoopStart $r0, 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $d0, $d2, $p0, $p1, $p2, $x0, $d1_3d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x2, renamable $p0 = VLDA_dmx_lda_x_pstm_nrm_imm killed renamable $p0, 64
; CHECK-NEXT: renamable $x4, dead renamable $r16 = VMAX_LT_32_vaddSign1 killed renamable $x2, renamable $x0, implicit $vaddsign1
; CHECK-NEXT: renamable $p1 = VST_dmx_sts_x_pstm_nrm_imm killed renamable $x4, killed renamable $p1, 64
; CHECK-NEXT: PseudoLoopEnd <mcsymbol .L_1120>, %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: PseudoRET implicit $lr
bb.0.entry:
successors: %bb.1
liveins: $r0, $p0, $p1, $x0
%0:ep = COPY $p0
%1:vec512 = COPY $x0
%2:ep = COPY $p1
LoopStart $r0, 0
bb.1:
successors: %bb.1, %bb.2
liveins: $p0, $p1, $p2, $d0, $d1_3d, $d2
%10:vec512, %0:ep = VLDA_dmx_lda_x_pstm_nrm_imm %0, 64
%11:vec512, %12:mr16_vcompare = VMAX_LT_32_vaddSign1 %10, %1, implicit $vaddsign1
%2:ep = VST_dmx_sts_x_pstm_nrm_imm %11, %2, 64
PseudoLoopEnd <mcsymbol .L_1120>, %bb.1
bb.2:
PseudoRET implicit $lr
...
34 changes: 18 additions & 16 deletions llvm/test/CodeGen/AIE/aie2p/schedule/postpipeliner/end-to-end.ll
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Expand Up @@ -20,27 +20,29 @@ define <32 x i16> @zol(i32 %n, ptr %p) {
; CHECK-NEXT: add.nc lc, r0, #-7
; CHECK-NEXT: movxm ls, #.LBB0_1
; CHECK-NEXT: movxm le, #.L_LEnd0
; CHECK-NEXT: nopa ; vldb x2, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: nopa ; vldb x2, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: nopa ; vldb x2, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: nopa ; vldb x2, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: nopa ; vldb x2, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: nopa ; vldb x2, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: nopa ; vldb x2, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: // implicit-def: $x0
; CHECK-NEXT: nopa ; vldb x0, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: nopa ; vldb x0, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: nopa ; vldb x0, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: nopa ; vldb x0, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: nopa ; vldb x0, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: nopa ; vldb x0, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: nopa ; vldb x0, [p0], #64; nops ; nopxm ; nopv
; CHECK-NEXT: // implicit-def: $x2
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: // %for.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: .L_LEnd0:
; CHECK-NEXT: nopa ; vldb x2, [p0], #64; nops ; nopx ; vadd.16 x0, x2, x0; nopv
; CHECK-NEXT: nopa ; vldb x0, [p0], #64; nops ; nopx ; vadd.16 x2, x0, x2; nopv
; CHECK-NEXT: // %bb.2: // %for.cond.cleanup
; CHECK-NEXT: nopa ; nopx ; vadd.16 x0, x2, x0
; CHECK-NEXT: vadd.16 x0, x2, x0
; CHECK-NEXT: vadd.16 x0, x2, x0
; CHECK-NEXT: vadd.16 x0, x2, x0
; CHECK-NEXT: vadd.16 x0, x2, x0
; CHECK-NEXT: vadd.16 x0, x2, x0
; CHECK-NEXT: vadd.16 x0, x2, x0
; CHECK-NEXT: vadd.16 x2, x0, x2
; CHECK-NEXT: vadd.16 x2, x0, x2
; CHECK-NEXT: vadd.16 x2, x0, x2
; CHECK-NEXT: vadd.16 x2, x0, x2
; CHECK-NEXT: vadd.16 x2, x0, x2
; CHECK-NEXT: vadd.16 x2, x0, x2
; CHECK-NEXT: vadd.16 x2, x0, x2
; CHECK-NEXT: nop
; CHECK-NEXT: vmov x0, x2
; CHECK-NEXT: ret lr
; CHECK-NEXT: nop // Delay Slot 5
; CHECK-NEXT: nop // Delay Slot 4
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