RapidWright 2024.1.3-beta Release

Release Notes:

• [RWRoute] Further cleanup (#1070)
• [PhysNetlistReader] Call SiteInst.setDesign() even for STATIC_SOURCEs (#1071)
• [GlobalSignalRouting] Fix VCC routing for UltraScale (#1068)
• [RWRoute] Cleanup static router and RouterHelper (#1059)
• [PartialRouter] Disable ripup in global/static routing (#1067)
• [TestDesign] Add test for net ordering of >= 2022.1 DCPs (#1054)
• [TestBEL] Add testDIFFsAreNotFF() (#1062)
• Test for Design.retargetPart() (#1061)
• [EDIF] Fixes rare bus renaming collision (#1065)
• [RWRoute] Always clear prev pointer of unpreserved RouteNode-s (#1056)
• [LaunchTestsOnLsf] Invoke java with assertions enabled (#1066)
• [LaunchTestsOnLsf] Invoke java with assertions enabled (#1063)
• Fix testRouteStaticNet() to avoid site pins, and fix golden values (#1064)
• [GitHub Actions] Migrate to upload-artifact@v4 (#1058)
• Add recursive partitioning ternary tree (RPTT) (#1055)
• Add support for vu19p tiles in bitstream
• [Design] createModuleInst() to not create duplicate STATIC_SOURCE-s
• Removes all instances of enum.hashCode()
• [Node] equals() to use instanceof for subclass-awareness
• Retarget & relocate an existing design to a new part and location
• Fixes issue related to non-deterministic Net order upon multi-threaded DCP load
• Fix BEL.isFF() based on BELTypes
• Fix missing Design.getSeries()

API Additions:

• com.xilinx.rapidwright.design.Design "public boolean retargetPart(Part targetPart, int tileXOffset, int tileYOffset)"

RapidWright 2024.1.2-beta Release

Release Notes:

• Creating a standalone entry point to relocate DCPs (#1047)
• [Interchange] Reorders tile types and tiles to follow their Vivado index (#1039)
• [DesignTools] Conform to Vivado RST pin inversion site routing configuration (#1053)
• Fix for design merging, including designs with encrypted cells (#1035)
• Filters out comments in XDC while parsing clk constraints (#1037)
• Assign an empty list when path finding for direct connections fails (#1052)
• Make LogicalNetlistToEdif not expand macros by default (#1051)
• [Interchange] Fixes to support Versal designs via Interchange (#1040)
• EDIF cleanup preventing singleton cells/libraries from attaching to user designs (#1050)
• [RWRoute] Refactoring/cleanup/preparation for multi-threading (#1046)
• Add Hybrid Updating Strategy (HUS) (#1043)
• [TestSiteInst] Add test for unrouting through FF routethru cells (#1041)
• [TestPIP] Test PIP constructor for reversed wires (#1045)
• [RWRoute] Preserve primary source nodes on connections (#1038)
• Small Interchange/PhysNetlistReader/VivadoTools improvements (#1042)
• [UnisimManager] Use EDIFLibraryBuiltin for primitive/macro libs
• Avoids NPE when site routing BRAMs
• Fix isCarry() for Versal devices
• Resolves PIP constructor issue for reversed PIPs
• [SiteInst] unrouteIntraSiteNet() to handle FF routethru cells

API Additions:

• com.xilinx.rapidwright.design.Design "public Series getSeries()"
• com.xilinx.rapidwright.design.SiteInst "public SitePIP getUsedSitePIP(BEL bel)"

RapidWright 2024.1.1-beta Release

Release Notes:

• [VivadoTools] Source *_load.tcl from same dir as DCP (#1032)
• Test that PIP.isReversed() is correct (#1024)
• Add TestSite.testGetIntTile() (#1022)
• [EDIFTools] writeTclLoadScriptForPartialEncryptedDesigns abspath (#1029)
• Adding HDIOB types (#1028)
• Test for site routing from raw placed design (#1000)
• [RWRoute] Do not NPE on encrypted netlists (#1025)
• [RWRoute] Do not assume Y = 0 has Laguna tiles, since it could be HBM device (#1026)
• Adds UNKWN state for LSFJobs (#1027)
• Adding legacy support for u280 (#1021)
• Remove flawed loop intended to for encrypted cell removal (#1023)
• [DesignTools.makeBlackBox()] Fixes an issue of removing CARRY blocks fed by routethrus (#1009)
• Fix null netlist pointer on expanded macro children (#1008)
• [Interchange] Device Resources Verifier Fixes (#1014)
• Fix ConcurrentModificationError (#1015)
• [EDIFTools] Adding method to create a flat netlist from a hierarchical one (#1006)
• Adding HBM ComponentTypes (#1007)
• Test for wire/node mismatch reported in #983 (#1005)
• 3.6% memory reduction usage for large placed designs (de-duplication of cell pin strings)
• Add missing pin entry for BUFG_GT when tracking INT tile connections
• Fixes rare DCP write issue with stubbed bi-directional PIPs (more common on DFX designs)
• Fix for reversed flag on PIPs
• Addresses issue with Net.getBufferDelay() by checking for null wire names
• Fixes two site routing issues

RapidWright 2024.1.0-beta Release

Release Notes:
Notes:

• Support for Vivado 2024.1 DCPs and devices
• Support to write DCPs with physDB components with Params.RW_WRITE_DCP_2024_1
• 2024.1 DCP Write Test (#997)
• Updates to support 2024.1 DCP writing (#995)
• Add FileTools.getAutoBufferedInputStream() with zstd auto-detect (#990)
• BlockPlacer2: Fix off by one error in selecting module instance to move (#987)
• Fix PolynomialGenerator and TestDCPSave tests (#982)
• Use exit code 1 if any LSF job failed (#981)
• Fixes issues around Node->Wire equivalence (#407)

API Additions:

• com.xilinx.rapidwright.device.Device "public boolean hasModularSLRs()"
• com.xilinx.rapidwright.device.Wire "public boolean isConnected()"
• com.xilinx.rapidwright.device.Wire "public boolean isTiedToVCC()"
• com.xilinx.rapidwright.device.Wire "public boolean isTiedToGND()"
• com.xilinx.rapidwright.device.Wire "public boolean isTied()"

API Removals:

• com.xilinx.rapidwright.device.Node "public int getWire()"
• com.xilinx.rapidwright.util.RapidWright "*"

RapidWright 2023.2.2-beta Release

Release Notes:
Notes:

• Use new Cell.{LOCKED,PORT_TYPE,isPortCell()} (#977)
• Remove some pre-2023.2.2 workarounds (#978)
• [RWRoute] Fix logical driver flag setting for DCP write (#979)
• Add explicit use case for a Jython script in --help (#980)
• [VivadoTools] Add placeDesign() and getWorstSetupSlack() (#975)
• [RWRoute] Consider all nets in timing-driven routing (#976)
• [DCP] Test Design.writeCheckpoint() when using existing EDIF (#965)
• Work around for multi-inverter BEL in DSP58 (#969)
• [DesignTools.makeBlackBox()] Fix for #967 (#970)
• [RWRoute,PhysNetlistReader] Set logical driver on PIPs (#973)
• [SLRCrosserGenerator] Adds North/South parameterizable bus widths; some error checking (#972)
• [EDIFTokenizer] Account for byte size of UTF-8 characters correctly (#962)
• [VivadoTools] writeBitstream to not delete DCP parent dir (+more) (#955)
• [RWRoute] Preserve [A-H]_O node when [A-H]MUX used as static src (#954)
• [GlobalSignalRouter] No intra site routing for new static source pins (#953)
• [EDIFPropertyValue] Fix getBooleanValue() NPE (#952)
• [PhysNetlistReader] Fix checkConstantRoutingAndNetNaming() (#951)
• [RWRoute] When removing unused source SPI restore intra-site routing (#949)
• [RWRoute] Tidy up createNetWrapperAndConnections() (#950)
• Fix EDIFPropertyValue.getBooleanValue() (#948)
• [RWRoute] Replace main src with altsrc if main is unused (#945)
• [RWRoute] Fix comment Eastern -> Western (#943)
• RouterHelper.invertPossibleGndPinsToVccPins() to invert static LUT inputs (#910)
• [TestRWRoute] Stop skipping some tests when < 8GB (#941)
• Temporary workaround to clear logical net after Net.rename() (#942)
• Known failing test for EDIFHierPortInst.getRoutedSitePinInst() (#577)
• Known failing test for Tile.getSites() result different to Vivado (#745)
• Known failing test for BITSLICE_CONTROL output pin projection (#559)
• Add known failing testcase for #756 (#758)
• Update RWRouteConfig.java (#940)
• [RWRoute] Add --lutRoutethru option (#932)
• [RWRoute] Do not pin swap SRL (shift register) cells (#939)
• [LUTTools] LUT pin swapping fixes (#938)
• Net.rename() to clear logical hier net
• Fix regarding issue around bitstream header
• Fixes issue when site wire lacks GND tag

API Additions:

• com.xilinx.rapidwright.bitstream.Bitstream "public boolean writeBitstream(Path path)"
• com.xilinx.rapidwright.bitstream.Frame "public List getDiff(Frame otherFrame)"
• com.xilinx.rapidwright.design.Cell "public static final String LOCKED = "";
• com.xilinx.rapidwright.design.Cell "public static final String PORT_TYPE = "";
• com.xilinx.rapidwright.design.Cell "public boolean isPortCell()"
• com.xilinx.rapidwright.design.Cell "public String getPropertyValueString(String key)"
• com.xilinx.rapidwright.design.Design "public void writeCheckpoint(String dcpFileName, String edfFileName, CodePerfTracker t)"
• com.xilinx.rapidwright.design.Design "public void writeCheckpoint(Path dcpFileName, Path edfFileName, CodePerfTracker t)"
• com.xilinx.rapidwright.design.Design "public void detachNetlist(Predicate preserveCellProperties)"
• com.xilinx.rapidwright.device.BEL "public static BEL getBEL(Device device, SiteTypeEnum siteTypeEnum, String belName)"
• com.xilinx.rapidwright.device.PIP "public boolean isArcInverted()"
• com.xilinx.rapidwright.device.PIP "public void setIsLogicalDriver(boolean isLogicalDriver)"
• com.xilinx.rapidwright.device.SitePIP "public int getIndex()"
• com.xilinx.rapidwright.device.SitePIP "public static SitePIP getSitePIP(Device device, SiteTypeEnum siteTypeEnum, int sitePIPIndex)"

RapidWright 2023.2.1-beta Release

Release Notes:

• Add EDIFHierCellInst.isUniquified() (#918)
• [RWRoute] RouteNode to extend Node (#916)
• [DesignComparator] Fix whitespace (#937)
• RouteThruHelper.isRouteThruPIPAvailable(Design, WireInterface, WireIn (#915)
• Create a common interface for Node and Wire Objects (#892)
• DesignComparator - compares place and route data (#931)
• DesignTools.createMissingSitePinInsts() to infer SitePinInsts more smartly (#936)
• LUTTools.swapLutPinsFromPIPs() to warn when site pin not found (#934)
• [PhysNetlistReader] Warn and omit if PIP not found (#933)
• [PhysNetlistWriter] Handle PORT cells in GTY tiles (#930)
• [PhysNetlistWriter] Assume static net output BELPins to be sources too (#929)
• [PhysNetlistWriter] Fix stubs on static nets (#928)
• Get a Boolean from EDIFPropertyValue (#926)
• [PhysNetlistWriter] Infer direction of IOB's PAD.PAD BEL pin (#927)
• [RouteThruHelper] Move assertions, improve tests (#925)
• [RWRoute] Don't swap dist RAMs on 'H' BELs since A and WA are shared (#924)
• [PhysNetlistWriter] Recognize static source BELPins (e.g. LUT outputs) (#923)
• [RWRoute] Analyze a tile below the topmost arbitrary one (#921)
• Adding test for IOB placement (#903)
• [DesignTools.makeBlackBox()] Fixes routing issues in makeBlackBox() (#919)
• [ECOTools] Inline cell insertion (#917)
• RouterHelper.invertPossibleGndPinsToVccPins() to work on all invertible pins (#911)
• [RWRoute] GlobalSignalRouting static net router to use [A-H]MUX outputs (#914)
• [RWRoute] Fix exception for unrouteable connections (#913)
• Declare gradle dependency explicitly (#909)
• Fixes [Versal BELAttr] Parsing issue #912
• Add site pins when site routing through inverter BELs
• Fix UltraScale+ IBUF site routing
• Fix DSP pin mapping removals during site routing
• Adds support for special clock Node flag present in Versal designs

API Additions:

• com.xilinx.rapidwright.device.Node "public Node(Node node)"
• com.xilinx.rapidwright.device.Package "public synchronized PackagePin getPackagePin(Site site)"
• com.xilinx.rapidwright.device.Package "public String getPackagePinName(Site site)"

RapidWright 2023.2.0-beta Release

Release Notes:

• SLR Corner updates in device models and handling (#886)
• Updates Protobuf to 3.25.0 (#882)
• Updates/adds timestamp APIs (#883)
• Refactor PROHIBIT constraint for faster Tcl interpretation (#881)
• [PerformanceExplorer] Number pblocks by order in file, add first site in dir name (#867)
• DesignTools.createMissingSitePinInsts(Design) to ignore GLOBAL_USEDNET (#880)
• [RWRoute] Check source & sink pin reaches INT tile for dedicated connections (#878)
• ECOTools.createExitSitePinInst() to detect net aliases (#871)
• Rewrite RouterHelper.projectOutputPinToINTNode() with fixes (#877)
• EDIFNetlist.{generateParentNetMap,getNetAliases}() to be inout-aware (#876)
• DesignTools.createMissingSitePinInsts() to cope with net aliases (#875)
• Improve TestECOPlacementHelper (#874)
• Add com.xilinx.rapidwright.eco.ECOPlacementHelper (#870)
• RouteThruHelper to handle SiteInst == null (#866)
• Add RouteThruHelper.isRouteThruPIPAvailable(Design, Node, Node) overload (#865)
• Add DesignTools.getConnectedBELPins() (#864)
• RelocationTools fixes and more robust testing (#863)
• Fix TimingAndWirelengthReport.main() (#860)
• [Tests] Symlinks to absolute paths (#862)
• added check to see if Cell.getLogicalPinMapping() is null (#783)
• [DCP] Update tests to infer SitePinInsts (#857)
• Replace $(shell ...) with $(wildcard) and $(subst) in Makefile (#856)
• Undpreccate Design.createCell()
• Special clock flag fix for Versal DCPs
• More conservative SitePinInst creation upon DCP load

API Additions:

• com.xilinx.rapidwright.design.SitePinInst "public int getConnectedTileWire()"
• com.xilinx.rapidwright.device.Device "public int getSiteIndex(String siteName)"
• com.xilinx.rapidwright.device.Device "public int getSiteIndex(Site site)"
• com.xilinx.rapidwright.device.Device "public Site getSiteByIndex(int siteIndex)"
• com.xilinx.rapidwright.device.Device "public Site[] getAllSites()"

API Removals:

• com.xilinx.rapidwright.bitstream.ConfigRow "public ConfigRow()"

RapidWright 2023.1.4-beta Release

Release Notes:

• Include RapidWright API Lib Javadoc in Gradle Build (#855)
• Add com.xilinx.rapidwright.eco.ECOTools package (#850)
• More Polynomial Generator improvements (#854)
• ReportRouteStatusResult.isFullyRouted() to check >0 logical net found (#852)
• Fixes for the PolynomialGenerator (tutorial) (#846)
• Test that Design.createModuleInst() copies static sources (#839)
• ModuleInst.place() to check both RAMB36/RAMB18 sites for overlap (#841)
• PartialRouter preprocessing and clock routing improvements (#843)
• Updates to Interchange README.md (#832)
• Simplify and make DesignTools.updatePinsIsRouted() more robust (#844)
• RouterHelper.invertPossibleGndPinsToVccPins() to not invert BRAM CLKs (#840)
• ModuleInst.connect() to leave physical Net alone for pass-thrus (#722)
• Unroute site routing when removing a cell (#729)
• PartialRouter's global router to not unpreserve sink nodes (#736)
• DesignTools.makePhysNetNamesConsistent() to use hier name (#735)
• DesignTools.makePhysNetNamesConsistent() to consider */<const{0,1}> (#734)
• Add DcpToInterchange class (#704)
• Add compile step (#733)
• Add EdifToLogicalNetlist to MainEntrypoint (#731)
• [PhysNetlistReader] Set Cell type for routethru cells (#727)
• Fix Javadoc warnings (#723)
• Fixes an issue with makeBlackBox trying to remove pins from renamed nets (#728)
• Multilevel macro expansion (#726)
• TestReplaceEDIFInDCP to copy DCP before replacing in-place (#725)
• DesignTools.createMissingSitePinInsts() to skip node-less site pins (#724)
• Add missing Versal DSP SiteTypeEnum (#842)
• [RWRoute] Further fix/cleanup around alternate source pins (#830)
• Adding out-of-context flag to RWRoute (#836)
• fix a bug in PipelineGeneratorWithRouting.createPipeline() (#837)
• Fix verb tense in RWRoute INFO msg (#835)
• Enable RWRoute to load Interchange designs from main() (#834)
• [VivadoTools] Check for Vivado on PATH first (#831)
• [EDIFNetlist] - Ensure Macro Expansion Deep Copies Children (#828)
• Minor RWRoute and UltraScaleClockRouting fixes (#829)
• Properly add/remove dual-output pins (#825)
• [TestRouteNode] Update comment; swap east and west (#827)
• Add VivadoTools.reportRouteStatus() overload for specific net status (#823)
• Update link to Discussions forum (#824)
• [RWRoute] Only add alternative sources to SiteInst if used (#821)
• RouteNode.getPIPsBackToSource() to recognize reversed PIPs (#822)
• [PhysNetlistReader] Create FFRoutethruCell-s correctly (#817)
• Add test for Design.movePinsToNewNetDeleteOldNet() (#796)
• Test Cell.getAllCorrespondingSitePinNames() works for multi-outputs (#792)
• [PhysNetlistWriter] No IO site port output BELPins without SitePinInst (#820)
• [PhysNetlistWriter] Set PhysPip.setForward() even if not bidir (#819)
• [PhysNetlistWriter] Skip output BELPins without cells, and port cells (#818)
• Test that Design.createModuleInst() copies static sources (#839)
• Design.createModuleInst() to copy STATIC_SOURCE_ SiteInsts properly
• Store partname in netlist for new designs
• SiteInst.addPin() to trackChanges() when ?_O or ?MUX pin added
• Method parameter names preserved in API lib jar
• API Additions:
  • com.xilinx.rapidwright.design.Module "public Cell getCell(String cellName)"
  • com.xilinx.rapidwright.design.Net "public boolean isVCCNet()"
  • com.xilinx.rapidwright.design.Net "public boolean isGNDNet()"
  • com.xilinx.rapidwright.design.Net "public boolean isUsedNet()"

RapidWright 2023.1.3-beta Release

Release Notes:
Notes:

• Fix DesignTools.getConnectionPIPs() (#809)
• [PhysNetlistWriter] RouteBranchNode.getDrivers() to return input BelPin (#800)
• Adds site pins to example code generation for nets. (#807)
• Update to fixed microblazeAndILA_3pblocks.dcp (#808)
• [LogNetlistWriter] Refactor writeStrings method to be public static (#804)
• [VivadoTools] ReportRouteStatusResult to parse more stats (#805)
• EDIF improvements (#806)
• RWRoute improvements (#803)
• Adds a createBitstream() method to VivadoTools (#801)
• Small DesignTools improvements (#797)
• added static function that helps produce test nets (including PIPs) (#784)
• Add reference copy methods (#794)
• [RWRoute] Add alternate source pins and set source routed flags (#787)
• Adds support for RouteThru LUT equations and makes LUTEquationEvaluator public (#795)
• Fix TestDCPLoad to prevent issues with parallel testing (#793)
• [PhysNetlistWriter] Fix route tree construction for bidir PIPs (#791)
• VivadoTools.reportRouteStatus() to handle encrypted cells (#777)
• [PhysNetlistWriter] Insert site port BELPin before site pin (#790)
• fixed null pointer exception in getPhysicalNetFromPin() (#775)
• LUT cell companion helper methods (#764)
• Check for error situation RAPIDWRIGHT_PATH set but not CLASSPATH (#772)
• Set reversed flag on bi-directional PIPs used from end->start (#774)
• Fix RouterHelper.projectOutputPinToINTNode() for depop pins (#779)
• Make PartialRouter.getUnroutedPins() public (#778)
• FileTools.runCommand() - Adds ability to choose run directory (#769)
• [GlobalSignalRouting] Static router to not create site pin if exists (#768)
• RouteThru support for FFs in UltraScale architecture
• Fixes minor SitePinInst creation when reading a DCP
• Improvements to Net.rename() when tracking changes
• Design.detachNetlist() to detach routethru cells
• Adds reference copy APIs and ability to keep copies of modified
  SiteInsts and Nets
• Improvements to DCP reading compatibility for different flows
  within Vivado
• API Additions:
  • com.xilinx.rapidwright.bitstream.BitLocation "public int hashCode()"
  • com.xilinx.rapidwright.bitstream.BitLocation "public boolean equals(Object obj)"
  • com.xilinx.rapidwright.bitstream.Bitstream "public static Bitstream readBitstream(Path fileName)"
  • com.xilinx.rapidwright.bitstream.Block "public int getBit(BitLocation bit, Tile tile)"
  • com.xilinx.rapidwright.bitstream.Block "public boolean updateBit(BitLocation bit, Tile tile, int value, Block golden)"
  • com.xilinx.rapidwright.bitstream.ConfigRow "public ConfigRow(int configRowIdx)"
  • com.xilinx.rapidwright.bitstream.FAR "public Block getConfigBlock(int slrCfgOrder)"
  • com.xilinx.rapidwright.bitstream.Packet "public int hashCode()"
  • com.xilinx.rapidwright.bitstream.Packet "public boolean equals(Object obj)"
  • com.xilinx.rapidwright.design.Cell "public static final String FF_ROUTETHRU_TYPE"
  • com.xilinx.rapidwright.design.Cell "public Cell getReferenceCopy()"
  • com.xilinx.rapidwright.design.Cell "public boolean isFFRoutethruCell()"
  • com.xilinx.rapidwright.design.Design "public boolean isCopyingOriginalNetsRouting()"
  • com.xilinx.rapidwright.design.Design "public void setCopyingOriginalNetsRouting(boolean copyOrigNets)"
  • com.xilinx.rapidwright.design.Design "public Map<String, List> getOriginalNetRouting()"
  • com.xilinx.rapidwright.design.Design "public boolean isCopyingOriginalSiteInsts()"
  • com.xilinx.rapidwright.design.Design "public void setCopyingOriginalSiteInsts(boolean copyOrigSiteInsts)"
  • com.xilinx.rapidwright.design.Design "public Map<String, SiteInst> getOriginalSiteInsts()"
  • com.xilinx.rapidwright.design.Net "public List getCopyOfPIPs()"
  • com.xilinx.rapidwright.design.SiteInst "public void addPin(SitePinInst sitePinInst)"
  • com.xilinx.rapidwright.design.SiteInst "public SiteInst getReferenceCopy()"

RapidWright 2023.1.2-beta Release

Release Notes:

• Shell creation improvements to enable lock_design and timing closure preservation (#760)
• Adds a MakeBlackBox command line tool (#747)
• Removes the VCC A6 pin on 5LUT usages when removing cells (#741)
• Add DesignTools.getAllRoutedSitePinsFromPhysicalPin() (#755)
• Correctly update dual-output route flags when unrouting (#737)
• [PhysNetlistReader] Set cell type of LOCKED cells (#767)
• Updates RAM32X1S property to correct default (#751)
• [Interchange] PhysNetlistReader to create STATIC_SOURCE SiteInsts (#766)
• RWRoute Fixes (#765)
• GlobalSignalRouting.routeStaticNet() to create output SPIs (#761)
• DesignTools.createCeSrRstPinsToVCC() to skip non-SLICE FFs (#744)
• [PartialRouter] Improve incremental global routing (#759)
• GlobalSignalRouting fixes for routing to non clock-pins (#757)
• DesignTools.makePhysNetNamesConsistent() to merge static nets too (#753)
• [UltraScaleClockRouting] Reset RouteNode.parent (#752)
• Created parameterizable counter with an adder as a submodule (#713)
• [RWRoute] Fix PartialRouter for when clk node already unpreserved (#746)
• [Interchange] Fix PhysicalNetlist's MultiCellPinMapping (#743)
• Unroute site routing when removing a cell (#729)
• PartialRouter's global router to not unpreserve sink nodes (#736)
• DesignTools.makePhysNetNamesConsistent() to use hier name (#735)
• DesignTools.makePhysNetNamesConsistent() to consider */<const{0,1}> (#734)
• Add DcpToInterchange class (#704)
• Add compile step (#733)
• Add EdifToLogicalNetlist to MainEntrypoint (#731)
• Fix Javadoc warnings (#723)
• Fixes an issue with makeBlackBox trying to remove pins from renamed nets (#728)
• [PhysNetlistReader] Set Cell type for routethru cells (#727)
• Multilevel macro expansion (#726)
• TestReplaceEDIFInDCP to copy DCP before replacing in-place (#725)
• DesignTools.createMissingSitePinInsts() to skip node-less site pins (#724)
• Fix to create alternate source pins on dual output nets.
• Fixes incorrect Versal SLR corner tile entries
• Cell.getProperty() returns null if no EDIFCellInst found
• Cell.getAllSitePinsFromLogicalPin() to not return any null pins
• Cell.getAllCorrespondingSitePinNames() to not NPE if no physical pin mapping
• Cell.getCorrespondingSitePinName() to consider F?MUX routethrus
• API Additions:
  • com.xilinx.rapidwright.device.PIP "public boolean isLogicalDriver()"
  • com.xilinx.rapidwright.design.Cell "public String getCorrespondingSitePinName(String logicalPinName, String physPinName, List siteWires)"