Merge pull request #994 from Xilinx/2024.1.0

2024.1.0

.classpath

@@ -33,9 +33,9 @@
 	<classpathentry kind="lib" path="jars/kryo-5.2.1.jar"/>
 	<classpathentry kind="lib" path="jars/minlog-1.3.1.jar"/>
 	<classpathentry kind="lib" path="jars/jython-standalone-2.7.2.jar"/>
-	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2023.2.2.jar">
+	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.1.0.jar">
 		<attributes>
-			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2023.2.2-javadoc.jar!/"/>
+			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.1.0-javadoc.jar!/"/>
 		</attributes>
 	</classpathentry>
 	<classpathentry kind="lib" path="jars/jgrapht-core-1.3.0.jar"/>

.github/workflows/build.yml

@@ -5,7 +5,7 @@ on:
   pull_request:
 
 env:
-  RAPIDWRIGHT_VERSION: v2023.2.2-beta
+  RAPIDWRIGHT_VERSION: v2024.1.0-beta
 
 jobs:
   build:

RELEASE_NOTES.TXT

@@ -1,4 +1,27 @@
-============= RapidWright 2023.2.2-beta released on 2023-04-03 ================
+============= RapidWright 2024.1.0-beta released on 2024-06-11 ================
+Notes: 
+  - Support for Vivado 2024.1 DCPs and devices
+  - Support to write DCPs with physDB components with Params.RW_WRITE_DCP_2024_1
+  - 2024.1 DCP Write Test (#997)
+  - Updates to support 2024.1 DCP writing (#995)
+  - Add FileTools.getAutoBufferedInputStream() with zstd auto-detect (#990)
+  - BlockPlacer2: Fix off by one error in selecting module instance to move (#987)
+  - Fix PolynomialGenerator and TestDCPSave tests (#982)
+  - Use exit code 1 if any LSF job failed (#981)
+  - Fixes issues around Node->Wire equivalence (#407)
+
+API Additions:
+  - com.xilinx.rapidwright.device.Device "public boolean hasModularSLRs()"
+  - com.xilinx.rapidwright.device.Wire "public boolean isConnected()"
+  - com.xilinx.rapidwright.device.Wire "public boolean isTiedToVCC()"
+  - com.xilinx.rapidwright.device.Wire "public boolean isTiedToGND()"
+  - com.xilinx.rapidwright.device.Wire "public boolean isTied()"
+
+API Removals:
+  - com.xilinx.rapidwright.device.Node "public int getWire()"
+  - com.xilinx.rapidwright.util.RapidWright "*"
+
+============= RapidWright 2023.2.2-beta released on 2024-04-03 ================
 Notes:
   - Use new Cell.{LOCKED,PORT_TYPE,isPortCell()} (#977)
   - Remove some pre-2023.2.2 workarounds (#978)
@@ -54,7 +77,7 @@ API Additions:
   - com.xilinx.rapidwright.device.SitePIP "public static SitePIP getSitePIP(Device device, SiteTypeEnum siteTypeEnum, int sitePIPIndex)"
 
 
-============= RapidWright 2023.2.1-beta released on 2023-01-10 ================
+============= RapidWright 2023.2.1-beta released on 2024-01-10 ================
 Notes:
   - Add EDIFHierCellInst.isUniquified() (#918)
   - [RWRoute] RouteNode to extend Node (#916)

src/com/xilinx/rapidwright/design/Unisim.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Advanced Micro Devices, Inc.
@@ -33,7 +33,7 @@
 import com.xilinx.rapidwright.edif.EDIFLibrary;
 
 /**
- * Generated on: Fri Oct 20 23:25:44 2023
+ * Generated on: Wed May 01 19:57:08 MDT 2024
  * by: com.xilinx.rapidwright.release.UnisimParser
  *
  * Enumerates supported Unisim primitives that map to Xilinx devices.
@@ -653,6 +653,7 @@ public enum Unisim {
     ISERDESE2,
     ISERDESE3,
     ISERDES_NODELAY,
+    ISP2,
     JTAG_SIME2,
     KEEPER,
     KEY_CLEAR,
@@ -724,6 +725,7 @@ public enum Unisim {
     MMCME5,
     MMCM_ADV,
     MMCM_BASE,
+    MMI,
     MRMAC,
     MULT18X18,
     MULT18X18S,
@@ -1289,6 +1291,7 @@ public enum Unisim {
     RAMS64E5,
     RFADC,
     RFADC_13B4W_M0,
+    RFADC_13B4W_M1,
     RFDAC,
     RIU_OR,
     ROM128X1,
@@ -1334,6 +1337,7 @@ public enum Unisim {
     USR_ACCESS_VIRTEX6,
     VCC,
     VCU,
+    VCU2,
     VDU,
     X5PHIO_CMUIF,
     X5PHIO_CMU_X32,

src/com/xilinx/rapidwright/device/FamilyType.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Advanced Micro Devices, Inc.
@@ -27,7 +27,7 @@
 
 
 /**
- * Generated on: Fri Oct 20 21:29:57 2023
+ * Generated on: Wed May 01 19:03:12 MDT 2024
  * by: com.xilinx.rapidwright.release.PartNamePopulator
  *
  * Set of all Supported Xilinx families in RapidWright
@@ -40,6 +40,7 @@ public enum FamilyType {
         ARTIX7L,
         ARTIXUPLUS,
         ASPARTAN7,
+        AVERSALAIEDGE,
         AZYNQ,
         AZYNQUPLUS,
         KINTEX7,
@@ -74,7 +75,6 @@ public enum FamilyType {
         VIRTEXUPLUS,
         VIRTEXUPLUS58G,
         VIRTEXUPLUSHBM,
-        VIRTEXUPLUSHBMES1,
         ZYNQ,
         ZYNQUPLUS,
         ZYNQUPLUSRFSOC,

src/com/xilinx/rapidwright/device/Part.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Advanced Micro Devices, Inc.
@@ -30,7 +30,7 @@
 import java.util.HashSet;
 
 /**
- * Generated on: Fri Oct 20 21:29:57 2023
+ * Generated on: Wed May 01 19:03:12 MDT 2024
  * by: com.xilinx.rapidwright.release.PartNamePopulator
  *
  * Class used to uniquely represent a Xilinx part.
@@ -253,12 +253,12 @@ public Series getSeries() {
                 FamilyType.VIRTEXUPLUS,
                 FamilyType.VIRTEXUPLUS58G,
                 FamilyType.VIRTEXUPLUSHBM,
-                FamilyType.VIRTEXUPLUSHBMES1,
                 FamilyType.ZYNQUPLUS,
                 FamilyType.ZYNQUPLUSRFSOC,
         };
         ultraScalePlus = new HashSet<FamilyType>(Arrays.asList(ultraScalePlusTypes));
         versalTypes = new FamilyType[] {
+                FamilyType.AVERSALAIEDGE,
                 FamilyType.QRVERSALAICORE,
                 FamilyType.QVERSALAICORE,
                 FamilyType.QVERSALPREMIUM,

src/com/xilinx/rapidwright/device/PartNameTools.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Advanced Micro Devices, Inc.
@@ -36,7 +36,7 @@
 import com.xilinx.rapidwright.util.FileTools;
 
 /**
- * Generated on: Fri Oct 20 21:29:57 2023
+ * Generated on: Wed May 01 19:03:12 MDT 2024
  * by: com.xilinx.rapidwright.release.PartNamePopulator
  *
  * Class to hold utility APIs dealing with Parts and device names.
@@ -132,6 +132,7 @@ public static FamilyType getArchitectureFromFamilyType(FamilyType type) {
             case ARTIX7L: return FamilyType.ARTIX7;
             case ARTIXUPLUS: return FamilyType.KINTEXUPLUS;
             case ASPARTAN7: return FamilyType.SPARTAN7;
+            case AVERSALAIEDGE: return FamilyType.VERSAL;
             case AZYNQ: return FamilyType.ZYNQ;
             case AZYNQUPLUS: return FamilyType.ZYNQUPLUS;
             case KINTEX7: return FamilyType.KINTEX7;
@@ -165,7 +166,6 @@ public static FamilyType getArchitectureFromFamilyType(FamilyType type) {
             case VIRTEXUPLUS: return FamilyType.VIRTEXUPLUS;
             case VIRTEXUPLUS58G: return FamilyType.VIRTEXUPLUS58G;
             case VIRTEXUPLUSHBM: return FamilyType.VIRTEXUPLUSHBM;
-            case VIRTEXUPLUSHBMES1: return FamilyType.VIRTEXUPLUSHBM;
             case ZYNQ: return FamilyType.ZYNQ;
             case ZYNQUPLUS: return FamilyType.ZYNQUPLUS;
             case ZYNQUPLUSRFSOC: return FamilyType.ZYNQUPLUSRFSOC;
@@ -186,6 +186,7 @@ public static String getFullArchitectureName(FamilyType type) {
             case ARTIX7L: return "Artix-7";
             case ARTIXUPLUS: return "Kintex UltraScale+";
             case ASPARTAN7: return "Spartan-7";
+            case AVERSALAIEDGE: return "Versal ACAP";
             case AZYNQ: return "Zynq-7000";
             case AZYNQUPLUS: return "Zynq UltraScale+";
             case KINTEX7: return "Kintex-7";
@@ -220,7 +221,6 @@ public static String getFullArchitectureName(FamilyType type) {
             case VIRTEXUPLUS: return "Virtex UltraScale+";
             case VIRTEXUPLUS58G: return "Virtex UltraScale+";
             case VIRTEXUPLUSHBM: return "Virtex UltraScale+";
-            case VIRTEXUPLUSHBMES1: return "Virtex UltraScale+";
             case ZYNQ: return "Zynq-7000";
             case ZYNQUPLUS: return "Zynq UltraScale+";
             case ZYNQUPLUSRFSOC: return "Zynq UltraScale+ RFSOC";
@@ -241,6 +241,7 @@ public static Series getSeriesFromFamilyType(FamilyType type) {
             case ARTIX7L: return Series.Series7;
             case ARTIXUPLUS: return Series.UltraScalePlus;
             case ASPARTAN7: return Series.Series7;
+            case AVERSALAIEDGE: return Series.Versal;
             case AZYNQ: return Series.Series7;
             case AZYNQUPLUS: return Series.UltraScalePlus;
             case KINTEX7: return Series.Series7;
@@ -275,7 +276,6 @@ public static Series getSeriesFromFamilyType(FamilyType type) {
             case VIRTEXUPLUS: return Series.UltraScalePlus;
             case VIRTEXUPLUS58G: return Series.UltraScalePlus;
             case VIRTEXUPLUSHBM: return Series.UltraScalePlus;
-            case VIRTEXUPLUSHBMES1: return Series.UltraScalePlus;
             case ZYNQ: return Series.Series7;
             case ZYNQUPLUS: return Series.UltraScalePlus;
             case ZYNQUPLUSRFSOC: return Series.UltraScalePlus;

src/com/xilinx/rapidwright/device/TileTypeEnum.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Advanced Micro Devices, Inc.
@@ -27,7 +27,7 @@
 
 
 /**
- * Generated on: Fri Oct 20 23:25:44 2023
+ * Generated on: Wed May 01 19:57:08 MDT 2024
  * by: com.xilinx.rapidwright.release.SiteAndTileTypeUpdater
  *
  * Enumeration of TileTypeEnum type for all valid devices within Vivado.
@@ -626,6 +626,8 @@ public enum TileTypeEnum {
     GTH_DA7_TERM_L_RBRK,
     GTH_DA7_TERM_L_TERM_P,
     GTH_DA7_TERM_L_TERM_T,
+    GTH_DR1_TERM_L_FT,
+    GTH_DR1_TERM_L_TERM_B_FT,
     GTH_INT_INTERFACE,
     GTH_INT_INTERFACE_L,
     GTH_QUAD_HPIO_RBRK_FT,
@@ -636,6 +638,7 @@ public enum TileTypeEnum {
     GTH_QUAD_LEFT_FT,
     GTH_QUAD_LEFT_RBRK,
     GTH_QUAD_LEFT_RBRK_FT,
+    GTH_QUAD_LEFT_TERM_B_FT,
     GTH_QUAD_LEFT_TERM_T,
     GTH_QUAD_LEFT_TERM_T_FT,
     GTH_QUAD_RIGHT,
@@ -778,9 +781,14 @@ public enum TileTypeEnum {
     HDIO_HDIO_FILL_PCIE4_RBRK_FT,
     HDIO_HDIO_FILL_RBRK_FT,
     HDIO_HDIO_FILL_TERM_T_FT,
+    HDIO_HDIO_LEFT_TERM_T_FT,
     HDIO_HDIO_RIGHT_TERM_P_FT,
     HDIO_HDIO_RIGHT_TERM_RBRK_FT,
     HDIO_ILKN_RBRK_FT,
+    HDIO_OUTER_TERM_R_FT,
+    HDIO_OUTER_TERM_R_RBRK_FT,
+    HDIO_OUTER_TERM_R_TERM_B_FT,
+    HDIO_OUTER_TERM_R_TERM_T_FT,
     HDIO_PCIE4_RBRK_FT,
     HDIO_RIGHT_CFG_TERM_T,
     HDIO_RIGHT_RBRK,
@@ -806,7 +814,15 @@ public enum TileTypeEnum {
     HPIO_CFG_TERM_L_TOP_FT,
     HPIO_CFG_TOP_TERM_R,
     HPIO_CFG_TOP_TERM_R_GTH,
+    HPIO_GTH_AUX_IO_TERM_L_BOT_FT,
+    HPIO_GTH_AUX_IO_TERM_L_TOP_FT,
+    HPIO_GTH_CFG_TERM_L_BOT_FT,
+    HPIO_GTH_CFG_TERM_L_TOP_FT,
+    HPIO_GTH_QUAD_LEFT_RBRK_FT,
     HPIO_GTH_QUAD_RIGHT_RBRK_FT,
+    HPIO_GTH_TERM_L_M_RBRK_FT,
+    HPIO_GTH_TERM_L_RBRK_FT,
+    HPIO_GTH_TERM_L_TERM_T_FT,
     HPIO_HPIO_LEFT_TERM_B_L_FT,
     HPIO_HPIO_LEFT_TERM_P_FT,
     HPIO_HPIO_LEFT_TERM_T_L_FT,
@@ -991,6 +1007,7 @@ public enum TileTypeEnum {
     INT_INTF_LEFT_IBRK_IO_TERM_H_FT,
     INT_INTF_LEFT_IBRK_PCIE4_TERM_H_FT,
     INT_INTF_LEFT_IBRK_PCIE4_TERM_P_FT,
+    INT_INTF_LEFT_TERM_GT_IO_RBRK_FT,
     INT_INTF_LEFT_TERM_GT_TERM_H_FT,
     INT_INTF_LEFT_TERM_GT_TERM_P,
     INT_INTF_LEFT_TERM_H_FT,
@@ -1028,6 +1045,7 @@ public enum TileTypeEnum {
     INT_INTF_RIGHT_IO_TERM_B,
     INT_INTF_RIGHT_TERM_GT_IO_RBRK,
     INT_INTF_RIGHT_TERM_GT_TERM_H_FT,
+    INT_INTF_RIGHT_TERM_HDIO_FT,
     INT_INTF_RIGHT_TERM_H_FT,
     INT_INTF_RIGHT_TERM_IO,
     INT_INTF_RIGHT_TERM_IO_TERM_T,
@@ -1425,6 +1443,9 @@ public enum TileTypeEnum {
     RCLK_RCLK_DSP_INTF_DC12_L_FT,
     RCLK_RCLK_DSP_INTF_DC12_R_FT,
     RCLK_RCLK_GAP50_MINICBRK_FT,
+    RCLK_RCLK_HDIO_LAST_R_FT,
+    RCLK_RCLK_HDIO_R_FT,
+    RCLK_RCLK_HPIO_GTH_TERM_L_FT,
     RCLK_RCLK_HPIO_TERM_L_DA6_FT,
     RCLK_RCLK_HPIO_TERM_L_FT,
     RCLK_RCLK_IBRK_FSR2FE_FT,
@@ -1438,9 +1459,11 @@ public enum TileTypeEnum {
     RCLK_RCLK_INTF_LEFT_TERM_DA6_FT,
     RCLK_RCLK_INTF_LEFT_TERM_DA8_FT,
     RCLK_RCLK_INTF_LEFT_TERM_DC12_FT,
+    RCLK_RCLK_INTF_LEFT_TERM_GT_IO_FT,
     RCLK_RCLK_INTF_LEFT_TERM_IO_FT,
     RCLK_RCLK_INTF_LEFT_TERM_MX8_FT,
     RCLK_RCLK_INTF_PCIE3_LEFT_L_FT,
+    RCLK_RCLK_INTF_RIGHT_IBRK_PCIE4_R_FT,
     RCLK_RCLK_INTF_XIPHY_LEFT_L_FT,
     RCLK_RCLK_K3_TERM_L_FT,
     RCLK_RCLK_LAGUNA_L_FT,

src/com/xilinx/rapidwright/edif/EDIFNetlist.java

@@ -897,7 +897,7 @@ public EDIFHierPortInst getHierPortInstFromName(String hierPortInstName) {
      * @param name the hierarchical name
      * @return A pair of EdifHierCellInst and the unmatched portion of the name. The name may be null if we found a complete match
      */
-    private Pair<List<EDIFCellInst>, String> getHierObject(String name) {
+    public Pair<List<EDIFCellInst>, String> getHierObject(String name) {
         if (name.isEmpty()) return new Pair<>(Collections.singletonList(getTopCellInst()), null);
         String[] parts = name.split(EDIFTools.EDIF_HIER_SEP);